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Searched refs:IMX_PLL_BASE (Results 1 – 6 of 6) sorted by relevance

/openbmc/u-boot/arch/arm/cpu/arm926ejs/mx27/
H A Dgeneric.c46 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in clk_in_26m()
58 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in imx_get_mpllclk()
72 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in imx_get_armclk()
87 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in imx_get_ahbclk()
99 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in imx_get_spllclk()
118 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in imx_get_perclk1()
125 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in imx_get_perclk2()
132 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in imx_get_perclk3()
139 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in imx_get_perclk4()
181 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in cpu_eth_init()
H A Dtimer.c91 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in timer_init()
/openbmc/u-boot/arch/arm/lib/
H A Dasm-offsets.c80 DEFINE(CSCR, IMX_PLL_BASE + offsetof(struct pll_regs, cscr)); in main()
81 DEFINE(MPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, mpctl0)); in main()
82 DEFINE(SPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, spctl0)); in main()
83 DEFINE(PCDR0, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr0)); in main()
84 DEFINE(PCDR1, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr1)); in main()
85 DEFINE(PCCR0, IMX_PLL_BASE + offsetof(struct pll_regs, pccr0)); in main()
86 DEFINE(PCCR1, IMX_PLL_BASE + offsetof(struct pll_regs, pccr1)); in main()
/openbmc/u-boot/arch/arm/include/asm/arch-imx/
H A Dimx-regs.h49 #define IMX_PLL_BASE (0x1B000 + IMX_IO_BASE) macro
92 #define CSCR __REG(IMX_PLL_BASE) /* Clock Source Control Register */
101 #define MPCTL0 __REG(IMX_PLL_BASE + 0x4) /* MCU PLL Control Register 0 */
102 #define MPCTL1 __REG(IMX_PLL_BASE + 0x8) /* MCU PLL and System Clock Register 1 */
103 #define SPCTL0 __REG(IMX_PLL_BASE + 0xc) /* System PLL Control Register 0 */
104 #define SPCTL1 __REG(IMX_PLL_BASE + 0x10) /* System PLL Control Register 1 */
105 #define PCDR __REG(IMX_PLL_BASE + 0x20) /* Peripheral Clock Divider Register */
/openbmc/u-boot/board/armadeus/apf27/
H A Dfpga.c193 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in apf27_fpga_setup()
/openbmc/u-boot/arch/arm/include/asm/arch-mx27/
H A Dimx-regs.h195 #define IMX_PLL_BASE (0x27000 + IMX_IO_BASE) macro