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Searched refs:IMX7ULP_CLK_SPLL_PRE_DIV (Results 1 – 3 of 3) sorted by relevance

/openbmc/linux/include/dt-bindings/clock/
H A Dimx7ulp-clock.h18 #define IMX7ULP_CLK_SPLL_PRE_DIV 5 macro
/openbmc/u-boot/include/dt-bindings/clock/
H A Dimx7ulp-clock.h20 #define IMX7ULP_CLK_SPLL_PRE_DIV 5 macro
/openbmc/linux/drivers/clk/imx/
H A Dclk-imx7ulp.c78 …hws[IMX7ULP_CLK_SPLL_PRE_DIV] = imx_clk_hw_divider_flags("spll_pre_div", "spll_pre_sel", base + 0x… in imx7ulp_clk_scg1_init()