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Searched refs:IMX7ULP_CLK_SPLL_BUS_CLK (Results 1 – 4 of 4) sorted by relevance

/openbmc/linux/include/dt-bindings/clock/
H A Dimx7ulp-clock.h57 #define IMX7ULP_CLK_SPLL_BUS_CLK 43 macro
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dimx7ulp-pcc-clock.yaml105 <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx7ulp.dtsi281 <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
313 <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
/openbmc/linux/drivers/clk/imx/
H A Dclk-imx7ulp.c102 …hws[IMX7ULP_CLK_SPLL_BUS_CLK] = imx_clk_hw_divider_gate("spll_bus_clk", "spll_sel", CLK_SET_RATE_G… in imx7ulp_clk_scg1_init()