Searched refs:IMX7ULP_CLK_SOSC_BUS_CLK (Results 1 – 5 of 5) sorted by relevance
155 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;176 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;278 <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,287 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;310 <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
55 #define IMX7ULP_CLK_SOSC_BUS_CLK 41 macro
54 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
102 <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
124 …hws[IMX7ULP_CLK_SOSC_BUS_CLK] = imx_clk_hw_divider_gate("sosc_bus_clk", "sosc", 0, base + 0x104, 8… in imx7ulp_clk_scg1_init()