Searched refs:IMX7ULP_CLK_FIRC (Results 1 – 5 of 5) sorted by relevance
212 assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;222 assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;234 assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;246 assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;258 assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;282 assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;353 assigned-clocks-parents = <&clks IMX7ULP_CLK_FIRC>;417 assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;429 assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;441 assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;[all …]
167 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;336 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;349 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;361 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;373 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
16 #define IMX7ULP_CLK_FIRC 3 macro
65 hws[IMX7ULP_CLK_FIRC] = imx_get_clk_hw_by_name(np, "firc"); in imx7ulp_clk_scg1_init()111 …]->clk, hws[IMX7ULP_CLK_SYS_SEL]->clk, hws[IMX7ULP_CLK_SPLL_SEL]->clk, hws[IMX7ULP_CLK_FIRC]->clk); in imx7ulp_clk_scg1_init()113 …, hws[IMX7ULP_CLK_HSRUN_SYS_SEL]->clk, hws[IMX7ULP_CLK_SPLL_SEL]->clk, hws[IMX7ULP_CLK_FIRC]->clk); in imx7ulp_clk_scg1_init()