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Searched refs:IMX7ULP_CLK_DDR_DIV (Results 1 – 5 of 5) sorted by relevance

/openbmc/linux/include/dt-bindings/clock/
H A Dimx7ulp-clock.h45 #define IMX7ULP_CLK_DDR_DIV 32 macro
/openbmc/u-boot/include/dt-bindings/clock/
H A Dimx7ulp-clock.h47 #define IMX7ULP_CLK_DDR_DIV 32 macro
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dimx7ulp-pcc-clock.yaml97 <&scg1 IMX7ULP_CLK_DDR_DIV>,
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx7ulp.dtsi273 <&scg1 IMX7ULP_CLK_DDR_DIV>,
305 <&scg1 IMX7ULP_CLK_DDR_DIV>,
/openbmc/linux/drivers/clk/imx/
H A Dclk-imx7ulp.c115 …hws[IMX7ULP_CLK_DDR_DIV] = imx_clk_hw_divider_gate("ddr_clk", "ddr_sel", CLK_SET_RATE_PARENT | CLK… in imx7ulp_clk_scg1_init()