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Searched refs:IMX7D_PLL_ENET_MAIN_125M_CLK (Results 1 – 7 of 7) sorted by relevance

/openbmc/linux/include/dt-bindings/clock/
H A Dimx7d-clock.h51 #define IMX7D_PLL_ENET_MAIN_125M_CLK 42 macro
/openbmc/u-boot/include/dt-bindings/clock/
H A Dimx7d-clock.h55 #define IMX7D_PLL_ENET_MAIN_125M_CLK 42 macro
/openbmc/u-boot/arch/arm/dts/
H A Dimx7d.dtsi134 <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
H A Dimx7s.dtsi1111 <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx7d.dtsi208 <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
H A Dimx7s.dtsi1259 <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
/openbmc/linux/drivers/clk/imx/
H A Dclk-imx7d.c479 …hws[IMX7D_PLL_ENET_MAIN_125M_CLK] = imx_clk_hw_gate("pll_enet_125m_clk", "pll_enet_125m", base + 0… in imx7d_clocks_init()