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Searched refs:IMX6UL_CLK_PLL5_VIDEO_DIV (Results 1 – 4 of 4) sorted by relevance

/openbmc/u-boot/include/dt-bindings/clock/
H A Dimx6ul-clock.h65 #define IMX6UL_CLK_PLL5_VIDEO_DIV 52 macro
/openbmc/linux/include/dt-bindings/clock/
H A Dimx6ul-clock.h61 #define IMX6UL_CLK_PLL5_VIDEO_DIV 52 macro
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6ul-14x14-evk.dtsi266 assigned-clock-parents = <&clks IMX6UL_CLK_PLL5_VIDEO_DIV>;
/openbmc/linux/drivers/clk/imx/
H A Dclk-imx6ul.c238 …hws[IMX6UL_CLK_PLL5_VIDEO_DIV] = clk_hw_register_divider_table(NULL, "pll5_video_div", "pll5_post_… in imx6ul_clocks_init()