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Searched refs:IMX6UL_CLK_PLL5_POST_DIV (Results 1 – 3 of 3) sorted by relevance

/openbmc/u-boot/include/dt-bindings/clock/
H A Dimx6ul-clock.h64 #define IMX6UL_CLK_PLL5_POST_DIV 51 macro
/openbmc/linux/include/dt-bindings/clock/
H A Dimx6ul-clock.h60 #define IMX6UL_CLK_PLL5_POST_DIV 51 macro
/openbmc/linux/drivers/clk/imx/
H A Dclk-imx6ul.c236 hws[IMX6UL_CLK_PLL5_POST_DIV] = clk_hw_register_divider_table(NULL, "pll5_post_div", "pll5_video", in imx6ul_clocks_init()