Searched refs:IMX6UL_CLK_ENET_REF (Results 1 – 16 of 16) sorted by relevance
48 clocks = <&clks IMX6UL_CLK_ENET_REF>;
45 clocks = <&clks IMX6UL_CLK_ENET_REF>;
56 clocks = <&clks IMX6UL_CLK_ENET_REF>;
54 clocks = <&clks IMX6UL_CLK_ENET_REF>;
138 clocks = <&clks IMX6UL_CLK_ENET_REF>;
124 clocks = <&clks IMX6UL_CLK_ENET_REF>;
122 clocks = <&clks IMX6UL_CLK_ENET_REF>;
205 clocks = <&clks IMX6UL_CLK_ENET_REF>;
204 clocks = <&clks IMX6UL_CLK_ENET_REF>;
126 clocks = <&clks IMX6UL_CLK_ENET_REF>;
134 clocks = <&clks IMX6UL_CLK_ENET_REF>;
57 #define IMX6UL_CLK_ENET_REF 44 macro
53 #define IMX6UL_CLK_ENET_REF 44 macro
222 hws[IMX6UL_CLK_ENET_REF] = clk_hw_register_divider_table(NULL, "enet1_ref", "pll6_enet", 0, in imx6ul_clocks_init()525 clk_set_rate(hws[IMX6UL_CLK_ENET_REF]->clk, 50000000); in imx6ul_clocks_init()545 clk_set_parent(hws[IMX6UL_CLK_ENET1_REF_SEL]->clk, hws[IMX6UL_CLK_ENET_REF]->clk); in imx6ul_clocks_init()
776 <&clks IMX6UL_CLK_ENET_REF>,777 <&clks IMX6UL_CLK_ENET_REF>;
876 <&clks IMX6UL_CLK_ENET_REF>,877 <&clks IMX6UL_CLK_ENET_REF>;