Searched refs:IMX6SX_CLK_PLL5_VIDEO_DIV (Results 1 – 4 of 4) sorted by relevance
43 #define IMX6SX_CLK_PLL5_VIDEO_DIV 34 macro
47 #define IMX6SX_CLK_PLL5_VIDEO_DIV 34 macro
253 …hws[IMX6SX_CLK_PLL5_VIDEO_DIV] = clk_hw_register_divider_table(NULL, "pll5_video_div", "pll5_post_… in imx6sx_clocks_init()502 clk_set_parent(hws[IMX6SX_CLK_LCDIF1_PRE_SEL]->clk, hws[IMX6SX_CLK_PLL5_VIDEO_DIV]->clk); in imx6sx_clocks_init()
1316 assigned-clock-parents = <&clks IMX6SX_CLK_PLL5_VIDEO_DIV>,