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Searched refs:IMX6SX_CLK_PLL5_POST_DIV (Results 1 – 3 of 3) sorted by relevance

/openbmc/linux/include/dt-bindings/clock/
H A Dimx6sx-clock.h42 #define IMX6SX_CLK_PLL5_POST_DIV 33 macro
/openbmc/u-boot/include/dt-bindings/clock/
H A Dimx6sx-clock.h46 #define IMX6SX_CLK_PLL5_POST_DIV 33 macro
/openbmc/linux/drivers/clk/imx/
H A Dclk-imx6sx.c251 hws[IMX6SX_CLK_PLL5_POST_DIV] = clk_hw_register_divider_table(NULL, "pll5_post_div", "pll5_video", in imx6sx_clocks_init()