Searched refs:IMX6SLL_CLK_PLL2_BUS (Results 1 – 4 of 4) sorted by relevance
38 #define IMX6SLL_CLK_PLL2_BUS 25 macro
36 #define IMX6SLL_CLK_PLL2_BUS 25 macro
140 hws[IMX6SLL_CLK_PLL2_BUS] = imx_clk_hw_gate("pll2_bus", "pll2_bypass", base + 0x30, 13); in imx6sll_clocks_init()351 clk_set_parent(hws[IMX6SLL_CLK_PERIPH_PRE]->clk, hws[IMX6SLL_CLK_PLL2_BUS]->clk); in imx6sll_clocks_init()
137 <&clks IMX6SLL_CLK_PLL2_BUS>, <&clks IMX6SLL_CLK_ARM>,