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Searched refs:IMX6SLL_CLK_PLL2_BUS (Results 1 – 4 of 4) sorted by relevance

/openbmc/u-boot/include/dt-bindings/clock/
H A Dimx6sll-clock.h38 #define IMX6SLL_CLK_PLL2_BUS 25 macro
/openbmc/linux/include/dt-bindings/clock/
H A Dimx6sll-clock.h36 #define IMX6SLL_CLK_PLL2_BUS 25 macro
/openbmc/linux/drivers/clk/imx/
H A Dclk-imx6sll.c140 hws[IMX6SLL_CLK_PLL2_BUS] = imx_clk_hw_gate("pll2_bus", "pll2_bypass", base + 0x30, 13); in imx6sll_clocks_init()
351 clk_set_parent(hws[IMX6SLL_CLK_PERIPH_PRE]->clk, hws[IMX6SLL_CLK_PLL2_BUS]->clk); in imx6sll_clocks_init()
/openbmc/u-boot/arch/arm/dts/
H A Dimx6sll.dtsi137 <&clks IMX6SLL_CLK_PLL2_BUS>, <&clks IMX6SLL_CLK_ARM>,