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Searched refs:IMX6QDL_CLK_PLL4_POST_DIV (Results 1 – 5 of 5) sorted by relevance

/openbmc/u-boot/include/dt-bindings/clock/
H A Dimx6qdl-clock.h206 #define IMX6QDL_CLK_PLL4_POST_DIV 193 macro
/openbmc/linux/include/dt-bindings/clock/
H A Dimx6qdl-clock.h203 #define IMX6QDL_CLK_PLL4_POST_DIV 193 macro
/openbmc/u-boot/arch/arm/dts/
H A Dimx6qdl-sabreauto.dtsi248 <&clks IMX6QDL_CLK_PLL4_POST_DIV>;
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6qdl-sabreauto.dtsi261 <&clks IMX6QDL_CLK_PLL4_POST_DIV>;
/openbmc/linux/drivers/clk/imx/
H A Dclk-imx6q.c598 …hws[IMX6QDL_CLK_PLL4_POST_DIV] = clk_hw_register_divider_table(NULL, "pll4_post_div", "pll4_audio"… in imx6q_clocks_init()