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Searched refs:IMX6QDL_CLK_IPU2_DI0_PRE_SEL (Results 1 – 6 of 6) sorted by relevance

/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6q-logicpd.dts64 <&clks IMX6QDL_CLK_IPU2_DI0_PRE_SEL>;
H A Dimx6q-bx50v3.dtsi402 <&clks IMX6QDL_CLK_IPU2_DI0_PRE_SEL>,
/openbmc/u-boot/include/dt-bindings/clock/
H A Dimx6qdl-clock.h49 #define IMX6QDL_CLK_IPU2_DI0_PRE_SEL 37 macro
/openbmc/linux/include/dt-bindings/clock/
H A Dimx6qdl-clock.h46 #define IMX6QDL_CLK_IPU2_DI0_PRE_SEL 37 macro
/openbmc/u-boot/arch/arm/dts/
H A Dimx6q-logicpd.dts144 <&clks IMX6QDL_CLK_IPU2_DI0_PRE_SEL>;
/openbmc/linux/drivers/clk/imx/
H A Dclk-imx6q.c665 …hws[IMX6QDL_CLK_IPU2_DI0_PRE_SEL] = imx_clk_hw_mux_flags("ipu2_di0_pre_sel", base + 0x38, 6, 3, i… in imx6q_clocks_init()
934 clk_set_parent(hws[IMX6QDL_CLK_IPU2_DI0_PRE_SEL]->clk, hws[IMX6QDL_CLK_PLL5_VIDEO_DIV]->clk); in imx6q_clocks_init()