Searched refs:IMX6QDL_CLK_ENET_REF_SEL (Results 1 – 13 of 13) sorted by relevance
40 <&clks IMX6QDL_CLK_LDB_DI1_SEL>, <&clks IMX6QDL_CLK_ENET_REF_SEL>;
62 assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF_SEL>;
165 assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF_SEL>;
106 assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF_SEL>;
71 assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF_SEL>;
116 assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF_SEL>;
239 assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF_SEL>;
204 assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF_SEL>;
198 assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF_SEL>;
299 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_ENET_REF_SEL>;
1052 <&clks IMX6QDL_CLK_ENET_REF_SEL>;
276 #define IMX6QDL_CLK_ENET_REF_SEL 266 macro
918 hws[IMX6QDL_CLK_ENET_REF_SEL] = imx_clk_gpr_mux("enet_ref_sel", "fsl,imx6q-iomuxc-gpr", in imx6q_clocks_init()988 clk_set_parent(hws[IMX6QDL_CLK_ENET_REF_SEL]->clk, hws[IMX6QDL_CLK_ENET_REF]->clk); in imx6q_clocks_init()