| /openbmc/qemu/target/hexagon/mmvec/ |
| H A D | macros.h | 50 #define LOG_VTCM_BYTE(VA, MASK, VAL, IDX) \ argument 52 env->vtcm_log.data.ub[IDX] = (VAL); \ 54 set_bit((IDX), env->vtcm_log.mask); \ 56 clear_bit((IDX), env->vtcm_log.mask); \ 58 env->vtcm_log.va[IDX] = (VA); \ 73 #define fGENMASKW(QREG, IDX) \ argument 74 (((fGETQBIT(QREG, (IDX * 4 + 0)) ? 0xFF : 0x0) << 0) | \ 75 ((fGETQBIT(QREG, (IDX * 4 + 1)) ? 0xFF : 0x0) << 8) | \ 76 ((fGETQBIT(QREG, (IDX * 4 + 2)) ? 0xFF : 0x0) << 16) | \ 77 ((fGETQBIT(QREG, (IDX * 4 + 3)) ? 0xFF : 0x0) << 24)) [all …]
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| /openbmc/u-boot/arch/arm/include/asm/arch-imx8/sci/ |
| H A D | rpc.h | 20 #define RPC_I32(MSG, IDX) ((MSG)->DATA.i32[(IDX) / 4U]) argument 21 #define RPC_I16(MSG, IDX) ((MSG)->DATA.i16[(IDX) / 2U]) argument 22 #define RPC_I8(MSG, IDX) ((MSG)->DATA.i8[(IDX)]) argument 23 #define RPC_U32(MSG, IDX) ((MSG)->DATA.u32[(IDX) / 4U]) argument 24 #define RPC_U16(MSG, IDX) ((MSG)->DATA.u16[(IDX) / 2U]) argument 25 #define RPC_U8(MSG, IDX) ((MSG)->DATA.u8[(IDX)]) argument
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| /openbmc/qemu/target/hexagon/imported/mmvec/ |
| H A D | macros.def | 51 (((fGETQBIT(QREG,(IDX*4+0)) ? 0xFF : 0x0) << 0) 52 |((fGETQBIT(QREG,(IDX*4+1)) ? 0xFF : 0x0) << 8) 53 |((fGETQBIT(QREG,(IDX*4+2)) ? 0xFF : 0x0) << 16) 54 |((fGETQBIT(QREG,(IDX*4+3)) ? 0xFF : 0x0) << 24)), 72 ( fSXTN(4,8,(SRC >> (4*IDX)) & 0xF) ), 77 ( fSXTN(2,8,(SRC >> (2*IDX)) & 0x3) ), 82 ( (fGETCRUMB(IDX,SRC)>=0 ? (2-fGETCRUMB(IDX,SRC)) : fGETCRUMB(IDX,SRC) ) ), 89 (((fGETQBIT(QREG,(IDX*2+0)) ? 0xFF : 0x0) << 0) 90 |((fGETQBIT(QREG,(IDX*2+1)) ? 0xFF : 0x0) << 8)), 95 (VREG.w[IDX] & fGENMASKW((QREG),IDX)), [all …]
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| /openbmc/qemu/tests/tcg/hexagon/ |
| H A D | load_align.c | 87 #define LOAD_ur(SZ, RES, SHIFT, IDX) \ argument 91 : "r"(IDX)) 92 #define LOAD_ur_b(RES, SHIFT, IDX) \ argument 93 LOAD_ur(b, RES, SHIFT, IDX) 94 #define LOAD_ur_h(RES, SHIFT, IDX) \ argument 95 LOAD_ur(h, RES, SHIFT, IDX)
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| H A D | load_unpack.c | 96 #define BxW_LOAD_ur(SZ, RES, SHIFT, IDX) \ argument 100 : "r"(IDX)) 101 #define BxW_LOAD_ur_Z(RES, SHIFT, IDX) \ argument 102 BxW_LOAD_ur(ubh, RES, SHIFT, IDX) 103 #define BxW_LOAD_ur_S(RES, SHIFT, IDX) \ argument 104 BxW_LOAD_ur(bh, RES, SHIFT, IDX)
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| /openbmc/u-boot/common/ |
| H A D | dlmalloc.c | 870 #define frontlink(P, S, IDX, BK, FD) \ argument 874 IDX = smallbin_index(S); \ 875 mark_binblock(IDX); \ 876 BK = bin_at(IDX); \ 884 IDX = bin_index(S); \ 885 BK = bin_at(IDX); \ 887 if (FD == BK) mark_binblock(IDX); \
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| H A D | dlmalloc.src | 1735 #define frontlink(P, S, IDX, BK, FD) \ 1739 IDX = smallbin_index(S); \ 1740 mark_binblock(IDX); \ 1741 BK = bin_at(IDX); \ 1749 IDX = bin_index(S); \ 1750 BK = bin_at(IDX); \ 1752 if (FD == BK) mark_binblock(IDX); \
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| /openbmc/qemu/target/ppc/ |
| H A D | int_helper.c | 1691 #define ELEM_ADDR(VEC, IDX, SIZE) (&(VEC)->u8[IDX]) argument 1693 #define ELEM_ADDR(VEC, IDX, SIZE) (&(VEC)->u8[15 - (IDX)] - (SIZE) + 1) argument
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