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Searched refs:ICPU_TIMER_TICK_DIV (Results 1 – 5 of 5) sorted by relevance

/openbmc/u-boot/arch/mips/mach-mscc/include/mach/ocelot/
H A Docelot_icpu_cfg.h70 #define ICPU_TIMER_TICK_DIV 0xe8 macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/serval/
H A Dserval_icpu_cfg.h63 #define ICPU_TIMER_TICK_DIV 0xe0 macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/jr2/
H A Djr2_icpu_cfg.h70 #define ICPU_TIMER_TICK_DIV 0x108 macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/servalt/
H A Dservalt_icpu_cfg.h68 #define ICPU_TIMER_TICK_DIV 0xe8 macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/
H A Dddr.h390 writel(VCOREIII_TIMER_DIVIDER - 1, BASE_CFG + ICPU_TIMER_TICK_DIV); in sleep_100ns()