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Searched refs:ICPU_MEMCTRL_TIMING2_INIT_DLY (Results 1 – 5 of 5) sorted by relevance

/openbmc/u-boot/arch/mips/mach-mscc/include/mach/ocelot/
H A Docelot_icpu_cfg.h176 #define ICPU_MEMCTRL_TIMING2_INIT_DLY(x) ((x) & GENMASK(15, 0)) macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/serval/
H A Dserval_icpu_cfg.h179 #define ICPU_MEMCTRL_TIMING2_INIT_DLY(x) ((x) & GENMASK(15, 0)) macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/jr2/
H A Djr2_icpu_cfg.h186 #define ICPU_MEMCTRL_TIMING2_INIT_DLY(x) ((x) & GENMASK(15, 0)) macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/servalt/
H A Dservalt_icpu_cfg.h184 #define ICPU_MEMCTRL_TIMING2_INIT_DLY(x) ((x) & GENMASK(15, 0)) macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/
H A Dddr.h276 ICPU_MEMCTRL_TIMING2_INIT_DLY(VC3_MPAR_ID - 1)