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Searched refs:ICC_AP0R_EL1 (Results 1 – 1 of 1) sorted by relevance

/openbmc/qemu/hw/intc/
H A Darm_gicv3_kvm.c62 #define ICC_AP0R_EL1(n) \ macro
479 kvm_gicc_access(s, ICC_AP0R_EL1(3), ncpu, &reg64, true); in kvm_arm_gicv3_put()
481 kvm_gicc_access(s, ICC_AP0R_EL1(2), ncpu, &reg64, true); in kvm_arm_gicv3_put()
485 kvm_gicc_access(s, ICC_AP0R_EL1(1), ncpu, &reg64, true); in kvm_arm_gicv3_put()
489 kvm_gicc_access(s, ICC_AP0R_EL1(0), ncpu, &reg64, true); in kvm_arm_gicv3_put()
635 kvm_gicc_access(s, ICC_AP0R_EL1(3), ncpu, &reg64, false); in kvm_arm_gicv3_get()
637 kvm_gicc_access(s, ICC_AP0R_EL1(2), ncpu, &reg64, false); in kvm_arm_gicv3_get()
641 kvm_gicc_access(s, ICC_AP0R_EL1(1), ncpu, &reg64, false); in kvm_arm_gicv3_get()
645 kvm_gicc_access(s, ICC_AP0R_EL1(0), ncpu, &reg64, false); in kvm_arm_gicv3_get()