Searched refs:IBEX_SPI_HOST_INTR_STATE (Results 1 – 2 of 2) sorted by relevance
136 s->regs[IBEX_SPI_HOST_INTR_STATE] = 0x00; in ibex_spi_host_reset()172 uint32_t intr_state_reg = s->regs[IBEX_SPI_HOST_INTR_STATE]; in ibex_spi_host_irq()206 s->regs[IBEX_SPI_HOST_INTR_STATE] |= R_INTR_STATE_ERROR_MASK; in ibex_spi_host_irq()231 s->regs[IBEX_SPI_HOST_INTR_STATE] |= R_INTR_STATE_SPI_EVENT_MASK; in ibex_spi_host_irq()303 case IBEX_SPI_HOST_INTR_STATE...IBEX_SPI_HOST_INTR_ENABLE: in ibex_spi_host_read()358 case IBEX_SPI_HOST_INTR_STATE: in ibex_spi_host_write()
41 #define IBEX_SPI_HOST_INTR_STATE (0x00 / 4) /* rw1c */ macro