1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2013 - 2018 Intel Corporation. */
3 
4 #ifndef _IAVF_TYPE_H_
5 #define _IAVF_TYPE_H_
6 
7 #include "iavf_status.h"
8 #include "iavf_osdep.h"
9 #include "iavf_register.h"
10 #include "iavf_adminq.h"
11 #include "iavf_devids.h"
12 
13 #define IAVF_RXQ_CTX_DBUFF_SHIFT 7
14 
15 /* IAVF_MASK is a macro used on 32 bit registers */
16 #define IAVF_MASK(mask, shift) ((u32)(mask) << (shift))
17 
18 #define IAVF_MAX_VSI_QP			16
19 #define IAVF_MAX_VF_VSI			3
20 #define IAVF_MAX_CHAINED_RX_BUFFERS	5
21 
22 /* forward declaration */
23 struct iavf_hw;
24 typedef void (*IAVF_ADMINQ_CALLBACK)(struct iavf_hw *, struct iavf_aq_desc *);
25 
26 /* Data type manipulation macros. */
27 
28 #define IAVF_DESC_UNUSED(R)	\
29 	((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
30 	(R)->next_to_clean - (R)->next_to_use - 1)
31 
32 /* bitfields for Tx queue mapping in QTX_CTL */
33 #define IAVF_QTX_CTL_VF_QUEUE	0x0
34 #define IAVF_QTX_CTL_VM_QUEUE	0x1
35 #define IAVF_QTX_CTL_PF_QUEUE	0x2
36 
37 /* debug masks - set these bits in hw->debug_mask to control output */
38 enum iavf_debug_mask {
39 	IAVF_DEBUG_INIT			= 0x00000001,
40 	IAVF_DEBUG_RELEASE		= 0x00000002,
41 
42 	IAVF_DEBUG_LINK			= 0x00000010,
43 	IAVF_DEBUG_PHY			= 0x00000020,
44 	IAVF_DEBUG_HMC			= 0x00000040,
45 	IAVF_DEBUG_NVM			= 0x00000080,
46 	IAVF_DEBUG_LAN			= 0x00000100,
47 	IAVF_DEBUG_FLOW			= 0x00000200,
48 	IAVF_DEBUG_DCB			= 0x00000400,
49 	IAVF_DEBUG_DIAG			= 0x00000800,
50 	IAVF_DEBUG_FD			= 0x00001000,
51 	IAVF_DEBUG_PACKAGE		= 0x00002000,
52 
53 	IAVF_DEBUG_AQ_MESSAGE		= 0x01000000,
54 	IAVF_DEBUG_AQ_DESCRIPTOR	= 0x02000000,
55 	IAVF_DEBUG_AQ_DESC_BUFFER	= 0x04000000,
56 	IAVF_DEBUG_AQ_COMMAND		= 0x06000000,
57 	IAVF_DEBUG_AQ			= 0x0F000000,
58 
59 	IAVF_DEBUG_USER			= 0xF0000000,
60 
61 	IAVF_DEBUG_ALL			= 0xFFFFFFFF
62 };
63 
64 /* These are structs for managing the hardware information and the operations.
65  * The structures of function pointers are filled out at init time when we
66  * know for sure exactly which hardware we're working with.  This gives us the
67  * flexibility of using the same main driver code but adapting to slightly
68  * different hardware needs as new parts are developed.  For this architecture,
69  * the Firmware and AdminQ are intended to insulate the driver from most of the
70  * future changes, but these structures will also do part of the job.
71  */
72 enum iavf_mac_type {
73 	IAVF_MAC_UNKNOWN = 0,
74 	IAVF_MAC_XL710,
75 	IAVF_MAC_VF,
76 	IAVF_MAC_X722,
77 	IAVF_MAC_X722_VF,
78 	IAVF_MAC_GENERIC,
79 };
80 
81 enum iavf_vsi_type {
82 	IAVF_VSI_MAIN	= 0,
83 	IAVF_VSI_VMDQ1	= 1,
84 	IAVF_VSI_VMDQ2	= 2,
85 	IAVF_VSI_CTRL	= 3,
86 	IAVF_VSI_FCOE	= 4,
87 	IAVF_VSI_MIRROR	= 5,
88 	IAVF_VSI_SRIOV	= 6,
89 	IAVF_VSI_FDIR	= 7,
90 	IAVF_VSI_TYPE_UNKNOWN
91 };
92 
93 enum iavf_queue_type {
94 	IAVF_QUEUE_TYPE_RX = 0,
95 	IAVF_QUEUE_TYPE_TX,
96 	IAVF_QUEUE_TYPE_PE_CEQ,
97 	IAVF_QUEUE_TYPE_UNKNOWN
98 };
99 
100 #define IAVF_HW_CAP_MAX_GPIO		30
101 /* Capabilities of a PF or a VF or the whole device */
102 struct iavf_hw_capabilities {
103 	bool dcb;
104 	bool fcoe;
105 	u32 num_vsis;
106 	u32 num_rx_qp;
107 	u32 num_tx_qp;
108 	u32 base_queue;
109 	u32 num_msix_vectors_vf;
110 };
111 
112 struct iavf_mac_info {
113 	enum iavf_mac_type type;
114 	u8 addr[ETH_ALEN];
115 	u8 perm_addr[ETH_ALEN];
116 	u8 san_addr[ETH_ALEN];
117 	u16 max_fcoeq;
118 };
119 
120 /* PCI bus types */
121 enum iavf_bus_type {
122 	iavf_bus_type_unknown = 0,
123 	iavf_bus_type_pci,
124 	iavf_bus_type_pcix,
125 	iavf_bus_type_pci_express,
126 	iavf_bus_type_reserved
127 };
128 
129 /* PCI bus speeds */
130 enum iavf_bus_speed {
131 	iavf_bus_speed_unknown	= 0,
132 	iavf_bus_speed_33	= 33,
133 	iavf_bus_speed_66	= 66,
134 	iavf_bus_speed_100	= 100,
135 	iavf_bus_speed_120	= 120,
136 	iavf_bus_speed_133	= 133,
137 	iavf_bus_speed_2500	= 2500,
138 	iavf_bus_speed_5000	= 5000,
139 	iavf_bus_speed_8000	= 8000,
140 	iavf_bus_speed_reserved
141 };
142 
143 /* PCI bus widths */
144 enum iavf_bus_width {
145 	iavf_bus_width_unknown	= 0,
146 	iavf_bus_width_pcie_x1	= 1,
147 	iavf_bus_width_pcie_x2	= 2,
148 	iavf_bus_width_pcie_x4	= 4,
149 	iavf_bus_width_pcie_x8	= 8,
150 	iavf_bus_width_32	= 32,
151 	iavf_bus_width_64	= 64,
152 	iavf_bus_width_reserved
153 };
154 
155 /* Bus parameters */
156 struct iavf_bus_info {
157 	enum iavf_bus_speed speed;
158 	enum iavf_bus_width width;
159 	enum iavf_bus_type type;
160 
161 	u16 func;
162 	u16 device;
163 	u16 lan_id;
164 	u16 bus_id;
165 };
166 
167 #define IAVF_MAX_USER_PRIORITY		8
168 /* Port hardware description */
169 struct iavf_hw {
170 	u8 __iomem *hw_addr;
171 	void *back;
172 
173 	/* subsystem structs */
174 	struct iavf_mac_info mac;
175 	struct iavf_bus_info bus;
176 
177 	/* pci info */
178 	u16 device_id;
179 	u16 vendor_id;
180 	u16 subsystem_device_id;
181 	u16 subsystem_vendor_id;
182 	u8 revision_id;
183 
184 	/* capabilities for entire device and PCI func */
185 	struct iavf_hw_capabilities dev_caps;
186 
187 	/* Admin Queue info */
188 	struct iavf_adminq_info aq;
189 
190 	/* debug mask */
191 	u32 debug_mask;
192 	char err_str[16];
193 };
194 
195 /* RX Descriptors */
196 union iavf_16byte_rx_desc {
197 	struct {
198 		__le64 pkt_addr; /* Packet buffer address */
199 		__le64 hdr_addr; /* Header buffer address */
200 	} read;
201 	struct {
202 		struct {
203 			struct {
204 				union {
205 					__le16 mirroring_status;
206 					__le16 fcoe_ctx_id;
207 				} mirr_fcoe;
208 				__le16 l2tag1;
209 			} lo_dword;
210 			union {
211 				__le32 rss; /* RSS Hash */
212 				__le32 fd_id; /* Flow director filter id */
213 				__le32 fcoe_param; /* FCoE DDP Context id */
214 			} hi_dword;
215 		} qword0;
216 		struct {
217 			/* ext status/error/pktype/length */
218 			__le64 status_error_len;
219 		} qword1;
220 	} wb;  /* writeback */
221 };
222 
223 union iavf_32byte_rx_desc {
224 	struct {
225 		__le64  pkt_addr; /* Packet buffer address */
226 		__le64  hdr_addr; /* Header buffer address */
227 			/* bit 0 of hdr_buffer_addr is DD bit */
228 		__le64  rsvd1;
229 		__le64  rsvd2;
230 	} read;
231 	struct {
232 		struct {
233 			struct {
234 				union {
235 					__le16 mirroring_status;
236 					__le16 fcoe_ctx_id;
237 				} mirr_fcoe;
238 				__le16 l2tag1;
239 			} lo_dword;
240 			union {
241 				__le32 rss; /* RSS Hash */
242 				__le32 fcoe_param; /* FCoE DDP Context id */
243 				/* Flow director filter id in case of
244 				 * Programming status desc WB
245 				 */
246 				__le32 fd_id;
247 			} hi_dword;
248 		} qword0;
249 		struct {
250 			/* status/error/pktype/length */
251 			__le64 status_error_len;
252 		} qword1;
253 		struct {
254 			__le16 ext_status; /* extended status */
255 			__le16 rsvd;
256 			__le16 l2tag2_1;
257 			__le16 l2tag2_2;
258 		} qword2;
259 		struct {
260 			union {
261 				__le32 flex_bytes_lo;
262 				__le32 pe_status;
263 			} lo_dword;
264 			union {
265 				__le32 flex_bytes_hi;
266 				__le32 fd_id;
267 			} hi_dword;
268 		} qword3;
269 	} wb;  /* writeback */
270 };
271 
272 enum iavf_rx_desc_status_bits {
273 	/* Note: These are predefined bit offsets */
274 	IAVF_RX_DESC_STATUS_DD_SHIFT		= 0,
275 	IAVF_RX_DESC_STATUS_EOF_SHIFT		= 1,
276 	IAVF_RX_DESC_STATUS_L2TAG1P_SHIFT	= 2,
277 	IAVF_RX_DESC_STATUS_L3L4P_SHIFT		= 3,
278 	IAVF_RX_DESC_STATUS_CRCP_SHIFT		= 4,
279 	IAVF_RX_DESC_STATUS_TSYNINDX_SHIFT	= 5, /* 2 BITS */
280 	IAVF_RX_DESC_STATUS_TSYNVALID_SHIFT	= 7,
281 	/* Note: Bit 8 is reserved in X710 and XL710 */
282 	IAVF_RX_DESC_STATUS_EXT_UDP_0_SHIFT	= 8,
283 	IAVF_RX_DESC_STATUS_UMBCAST_SHIFT	= 9, /* 2 BITS */
284 	IAVF_RX_DESC_STATUS_FLM_SHIFT		= 11,
285 	IAVF_RX_DESC_STATUS_FLTSTAT_SHIFT	= 12, /* 2 BITS */
286 	IAVF_RX_DESC_STATUS_LPBK_SHIFT		= 14,
287 	IAVF_RX_DESC_STATUS_IPV6EXADD_SHIFT	= 15,
288 	IAVF_RX_DESC_STATUS_RESERVED_SHIFT	= 16, /* 2 BITS */
289 	/* Note: For non-tunnel packets INT_UDP_0 is the right status for
290 	 * UDP header
291 	 */
292 	IAVF_RX_DESC_STATUS_INT_UDP_0_SHIFT	= 18,
293 	IAVF_RX_DESC_STATUS_LAST /* this entry must be last!!! */
294 };
295 
296 #define IAVF_RXD_QW1_STATUS_SHIFT	0
297 #define IAVF_RXD_QW1_STATUS_MASK	((BIT(IAVF_RX_DESC_STATUS_LAST) - 1) \
298 					 << IAVF_RXD_QW1_STATUS_SHIFT)
299 
300 #define IAVF_RXD_QW1_STATUS_TSYNINDX_SHIFT IAVF_RX_DESC_STATUS_TSYNINDX_SHIFT
301 #define IAVF_RXD_QW1_STATUS_TSYNINDX_MASK  (0x3UL << \
302 					    IAVF_RXD_QW1_STATUS_TSYNINDX_SHIFT)
303 
304 #define IAVF_RXD_QW1_STATUS_TSYNVALID_SHIFT IAVF_RX_DESC_STATUS_TSYNVALID_SHIFT
305 #define IAVF_RXD_QW1_STATUS_TSYNVALID_MASK \
306 				    BIT_ULL(IAVF_RXD_QW1_STATUS_TSYNVALID_SHIFT)
307 
308 enum iavf_rx_desc_fltstat_values {
309 	IAVF_RX_DESC_FLTSTAT_NO_DATA	= 0,
310 	IAVF_RX_DESC_FLTSTAT_RSV_FD_ID	= 1, /* 16byte desc? FD_ID : RSV */
311 	IAVF_RX_DESC_FLTSTAT_RSV	= 2,
312 	IAVF_RX_DESC_FLTSTAT_RSS_HASH	= 3,
313 };
314 
315 #define IAVF_RXD_QW1_ERROR_SHIFT	19
316 #define IAVF_RXD_QW1_ERROR_MASK		(0xFFUL << IAVF_RXD_QW1_ERROR_SHIFT)
317 
318 enum iavf_rx_desc_error_bits {
319 	/* Note: These are predefined bit offsets */
320 	IAVF_RX_DESC_ERROR_RXE_SHIFT		= 0,
321 	IAVF_RX_DESC_ERROR_RECIPE_SHIFT		= 1,
322 	IAVF_RX_DESC_ERROR_HBO_SHIFT		= 2,
323 	IAVF_RX_DESC_ERROR_L3L4E_SHIFT		= 3, /* 3 BITS */
324 	IAVF_RX_DESC_ERROR_IPE_SHIFT		= 3,
325 	IAVF_RX_DESC_ERROR_L4E_SHIFT		= 4,
326 	IAVF_RX_DESC_ERROR_EIPE_SHIFT		= 5,
327 	IAVF_RX_DESC_ERROR_OVERSIZE_SHIFT	= 6,
328 	IAVF_RX_DESC_ERROR_PPRS_SHIFT		= 7
329 };
330 
331 enum iavf_rx_desc_error_l3l4e_fcoe_masks {
332 	IAVF_RX_DESC_ERROR_L3L4E_NONE		= 0,
333 	IAVF_RX_DESC_ERROR_L3L4E_PROT		= 1,
334 	IAVF_RX_DESC_ERROR_L3L4E_FC		= 2,
335 	IAVF_RX_DESC_ERROR_L3L4E_DMAC_ERR	= 3,
336 	IAVF_RX_DESC_ERROR_L3L4E_DMAC_WARN	= 4
337 };
338 
339 #define IAVF_RXD_QW1_PTYPE_SHIFT	30
340 #define IAVF_RXD_QW1_PTYPE_MASK		(0xFFULL << IAVF_RXD_QW1_PTYPE_SHIFT)
341 
342 /* Packet type non-ip values */
343 enum iavf_rx_l2_ptype {
344 	IAVF_RX_PTYPE_L2_RESERVED			= 0,
345 	IAVF_RX_PTYPE_L2_MAC_PAY2			= 1,
346 	IAVF_RX_PTYPE_L2_TIMESYNC_PAY2			= 2,
347 	IAVF_RX_PTYPE_L2_FIP_PAY2			= 3,
348 	IAVF_RX_PTYPE_L2_OUI_PAY2			= 4,
349 	IAVF_RX_PTYPE_L2_MACCNTRL_PAY2			= 5,
350 	IAVF_RX_PTYPE_L2_LLDP_PAY2			= 6,
351 	IAVF_RX_PTYPE_L2_ECP_PAY2			= 7,
352 	IAVF_RX_PTYPE_L2_EVB_PAY2			= 8,
353 	IAVF_RX_PTYPE_L2_QCN_PAY2			= 9,
354 	IAVF_RX_PTYPE_L2_EAPOL_PAY2			= 10,
355 	IAVF_RX_PTYPE_L2_ARP				= 11,
356 	IAVF_RX_PTYPE_L2_FCOE_PAY3			= 12,
357 	IAVF_RX_PTYPE_L2_FCOE_FCDATA_PAY3		= 13,
358 	IAVF_RX_PTYPE_L2_FCOE_FCRDY_PAY3		= 14,
359 	IAVF_RX_PTYPE_L2_FCOE_FCRSP_PAY3		= 15,
360 	IAVF_RX_PTYPE_L2_FCOE_FCOTHER_PA		= 16,
361 	IAVF_RX_PTYPE_L2_FCOE_VFT_PAY3			= 17,
362 	IAVF_RX_PTYPE_L2_FCOE_VFT_FCDATA		= 18,
363 	IAVF_RX_PTYPE_L2_FCOE_VFT_FCRDY			= 19,
364 	IAVF_RX_PTYPE_L2_FCOE_VFT_FCRSP			= 20,
365 	IAVF_RX_PTYPE_L2_FCOE_VFT_FCOTHER		= 21,
366 	IAVF_RX_PTYPE_GRENAT4_MAC_PAY3			= 58,
367 	IAVF_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4	= 87,
368 	IAVF_RX_PTYPE_GRENAT6_MAC_PAY3			= 124,
369 	IAVF_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4	= 153
370 };
371 
372 struct iavf_rx_ptype_decoded {
373 	u32 known:1;
374 	u32 outer_ip:1;
375 	u32 outer_ip_ver:1;
376 	u32 outer_frag:1;
377 	u32 tunnel_type:3;
378 	u32 tunnel_end_prot:2;
379 	u32 tunnel_end_frag:1;
380 	u32 inner_prot:4;
381 	u32 payload_layer:3;
382 };
383 
384 enum iavf_rx_ptype_outer_ip {
385 	IAVF_RX_PTYPE_OUTER_L2	= 0,
386 	IAVF_RX_PTYPE_OUTER_IP	= 1
387 };
388 
389 enum iavf_rx_ptype_outer_ip_ver {
390 	IAVF_RX_PTYPE_OUTER_NONE	= 0,
391 	IAVF_RX_PTYPE_OUTER_IPV4	= 0,
392 	IAVF_RX_PTYPE_OUTER_IPV6	= 1
393 };
394 
395 enum iavf_rx_ptype_outer_fragmented {
396 	IAVF_RX_PTYPE_NOT_FRAG	= 0,
397 	IAVF_RX_PTYPE_FRAG	= 1
398 };
399 
400 enum iavf_rx_ptype_tunnel_type {
401 	IAVF_RX_PTYPE_TUNNEL_NONE		= 0,
402 	IAVF_RX_PTYPE_TUNNEL_IP_IP		= 1,
403 	IAVF_RX_PTYPE_TUNNEL_IP_GRENAT		= 2,
404 	IAVF_RX_PTYPE_TUNNEL_IP_GRENAT_MAC	= 3,
405 	IAVF_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN	= 4,
406 };
407 
408 enum iavf_rx_ptype_tunnel_end_prot {
409 	IAVF_RX_PTYPE_TUNNEL_END_NONE	= 0,
410 	IAVF_RX_PTYPE_TUNNEL_END_IPV4	= 1,
411 	IAVF_RX_PTYPE_TUNNEL_END_IPV6	= 2,
412 };
413 
414 enum iavf_rx_ptype_inner_prot {
415 	IAVF_RX_PTYPE_INNER_PROT_NONE		= 0,
416 	IAVF_RX_PTYPE_INNER_PROT_UDP		= 1,
417 	IAVF_RX_PTYPE_INNER_PROT_TCP		= 2,
418 	IAVF_RX_PTYPE_INNER_PROT_SCTP		= 3,
419 	IAVF_RX_PTYPE_INNER_PROT_ICMP		= 4,
420 	IAVF_RX_PTYPE_INNER_PROT_TIMESYNC	= 5
421 };
422 
423 enum iavf_rx_ptype_payload_layer {
424 	IAVF_RX_PTYPE_PAYLOAD_LAYER_NONE	= 0,
425 	IAVF_RX_PTYPE_PAYLOAD_LAYER_PAY2	= 1,
426 	IAVF_RX_PTYPE_PAYLOAD_LAYER_PAY3	= 2,
427 	IAVF_RX_PTYPE_PAYLOAD_LAYER_PAY4	= 3,
428 };
429 
430 #define IAVF_RXD_QW1_LENGTH_PBUF_SHIFT	38
431 #define IAVF_RXD_QW1_LENGTH_PBUF_MASK	(0x3FFFULL << \
432 					 IAVF_RXD_QW1_LENGTH_PBUF_SHIFT)
433 
434 #define IAVF_RXD_QW1_LENGTH_HBUF_SHIFT	52
435 #define IAVF_RXD_QW1_LENGTH_HBUF_MASK	(0x7FFULL << \
436 					 IAVF_RXD_QW1_LENGTH_HBUF_SHIFT)
437 
438 #define IAVF_RXD_QW1_LENGTH_SPH_SHIFT	63
439 #define IAVF_RXD_QW1_LENGTH_SPH_MASK	BIT_ULL(IAVF_RXD_QW1_LENGTH_SPH_SHIFT)
440 
441 enum iavf_rx_desc_ext_status_bits {
442 	/* Note: These are predefined bit offsets */
443 	IAVF_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT	= 0,
444 	IAVF_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT	= 1,
445 	IAVF_RX_DESC_EXT_STATUS_FLEXBL_SHIFT	= 2, /* 2 BITS */
446 	IAVF_RX_DESC_EXT_STATUS_FLEXBH_SHIFT	= 4, /* 2 BITS */
447 	IAVF_RX_DESC_EXT_STATUS_FDLONGB_SHIFT	= 9,
448 	IAVF_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT	= 10,
449 	IAVF_RX_DESC_EXT_STATUS_PELONGB_SHIFT	= 11,
450 };
451 
452 enum iavf_rx_desc_pe_status_bits {
453 	/* Note: These are predefined bit offsets */
454 	IAVF_RX_DESC_PE_STATUS_QPID_SHIFT	= 0, /* 18 BITS */
455 	IAVF_RX_DESC_PE_STATUS_L4PORT_SHIFT	= 0, /* 16 BITS */
456 	IAVF_RX_DESC_PE_STATUS_IPINDEX_SHIFT	= 16, /* 8 BITS */
457 	IAVF_RX_DESC_PE_STATUS_QPIDHIT_SHIFT	= 24,
458 	IAVF_RX_DESC_PE_STATUS_APBVTHIT_SHIFT	= 25,
459 	IAVF_RX_DESC_PE_STATUS_PORTV_SHIFT	= 26,
460 	IAVF_RX_DESC_PE_STATUS_URG_SHIFT	= 27,
461 	IAVF_RX_DESC_PE_STATUS_IPFRAG_SHIFT	= 28,
462 	IAVF_RX_DESC_PE_STATUS_IPOPT_SHIFT	= 29
463 };
464 
465 #define IAVF_RX_PROG_STATUS_DESC_LENGTH_SHIFT		38
466 #define IAVF_RX_PROG_STATUS_DESC_LENGTH			0x2000000
467 
468 #define IAVF_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT	2
469 #define IAVF_RX_PROG_STATUS_DESC_QW1_PROGID_MASK	(0x7UL << \
470 				IAVF_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
471 
472 #define IAVF_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT	19
473 #define IAVF_RX_PROG_STATUS_DESC_QW1_ERROR_MASK		(0x3FUL << \
474 				IAVF_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
475 
476 enum iavf_rx_prog_status_desc_status_bits {
477 	/* Note: These are predefined bit offsets */
478 	IAVF_RX_PROG_STATUS_DESC_DD_SHIFT	= 0,
479 	IAVF_RX_PROG_STATUS_DESC_PROG_ID_SHIFT	= 2 /* 3 BITS */
480 };
481 
482 enum iavf_rx_prog_status_desc_prog_id_masks {
483 	IAVF_RX_PROG_STATUS_DESC_FD_FILTER_STATUS	= 1,
484 	IAVF_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS	= 2,
485 	IAVF_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS	= 4,
486 };
487 
488 enum iavf_rx_prog_status_desc_error_bits {
489 	/* Note: These are predefined bit offsets */
490 	IAVF_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT	= 0,
491 	IAVF_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT	= 1,
492 	IAVF_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT	= 2,
493 	IAVF_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT	= 3
494 };
495 
496 /* TX Descriptor */
497 struct iavf_tx_desc {
498 	__le64 buffer_addr; /* Address of descriptor's data buf */
499 	__le64 cmd_type_offset_bsz;
500 };
501 
502 #define IAVF_TXD_QW1_DTYPE_SHIFT	0
503 #define IAVF_TXD_QW1_DTYPE_MASK		(0xFUL << IAVF_TXD_QW1_DTYPE_SHIFT)
504 
505 enum iavf_tx_desc_dtype_value {
506 	IAVF_TX_DESC_DTYPE_DATA		= 0x0,
507 	IAVF_TX_DESC_DTYPE_NOP		= 0x1, /* same as Context desc */
508 	IAVF_TX_DESC_DTYPE_CONTEXT	= 0x1,
509 	IAVF_TX_DESC_DTYPE_FCOE_CTX	= 0x2,
510 	IAVF_TX_DESC_DTYPE_FILTER_PROG	= 0x8,
511 	IAVF_TX_DESC_DTYPE_DDP_CTX	= 0x9,
512 	IAVF_TX_DESC_DTYPE_FLEX_DATA	= 0xB,
513 	IAVF_TX_DESC_DTYPE_FLEX_CTX_1	= 0xC,
514 	IAVF_TX_DESC_DTYPE_FLEX_CTX_2	= 0xD,
515 	IAVF_TX_DESC_DTYPE_DESC_DONE	= 0xF
516 };
517 
518 #define IAVF_TXD_QW1_CMD_SHIFT	4
519 #define IAVF_TXD_QW1_CMD_MASK	(0x3FFUL << IAVF_TXD_QW1_CMD_SHIFT)
520 
521 enum iavf_tx_desc_cmd_bits {
522 	IAVF_TX_DESC_CMD_EOP			= 0x0001,
523 	IAVF_TX_DESC_CMD_RS			= 0x0002,
524 	IAVF_TX_DESC_CMD_ICRC			= 0x0004,
525 	IAVF_TX_DESC_CMD_IL2TAG1		= 0x0008,
526 	IAVF_TX_DESC_CMD_DUMMY			= 0x0010,
527 	IAVF_TX_DESC_CMD_IIPT_NONIP		= 0x0000, /* 2 BITS */
528 	IAVF_TX_DESC_CMD_IIPT_IPV6		= 0x0020, /* 2 BITS */
529 	IAVF_TX_DESC_CMD_IIPT_IPV4		= 0x0040, /* 2 BITS */
530 	IAVF_TX_DESC_CMD_IIPT_IPV4_CSUM		= 0x0060, /* 2 BITS */
531 	IAVF_TX_DESC_CMD_FCOET			= 0x0080,
532 	IAVF_TX_DESC_CMD_L4T_EOFT_UNK		= 0x0000, /* 2 BITS */
533 	IAVF_TX_DESC_CMD_L4T_EOFT_TCP		= 0x0100, /* 2 BITS */
534 	IAVF_TX_DESC_CMD_L4T_EOFT_SCTP		= 0x0200, /* 2 BITS */
535 	IAVF_TX_DESC_CMD_L4T_EOFT_UDP		= 0x0300, /* 2 BITS */
536 	IAVF_TX_DESC_CMD_L4T_EOFT_EOF_N		= 0x0000, /* 2 BITS */
537 	IAVF_TX_DESC_CMD_L4T_EOFT_EOF_T		= 0x0100, /* 2 BITS */
538 	IAVF_TX_DESC_CMD_L4T_EOFT_EOF_NI	= 0x0200, /* 2 BITS */
539 	IAVF_TX_DESC_CMD_L4T_EOFT_EOF_A		= 0x0300, /* 2 BITS */
540 };
541 
542 #define IAVF_TXD_QW1_OFFSET_SHIFT	16
543 #define IAVF_TXD_QW1_OFFSET_MASK	(0x3FFFFULL << \
544 					 IAVF_TXD_QW1_OFFSET_SHIFT)
545 
546 enum iavf_tx_desc_length_fields {
547 	/* Note: These are predefined bit offsets */
548 	IAVF_TX_DESC_LENGTH_MACLEN_SHIFT	= 0, /* 7 BITS */
549 	IAVF_TX_DESC_LENGTH_IPLEN_SHIFT		= 7, /* 7 BITS */
550 	IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT	= 14 /* 4 BITS */
551 };
552 
553 #define IAVF_TXD_QW1_TX_BUF_SZ_SHIFT	34
554 #define IAVF_TXD_QW1_TX_BUF_SZ_MASK	(0x3FFFULL << \
555 					 IAVF_TXD_QW1_TX_BUF_SZ_SHIFT)
556 
557 #define IAVF_TXD_QW1_L2TAG1_SHIFT	48
558 #define IAVF_TXD_QW1_L2TAG1_MASK	(0xFFFFULL << IAVF_TXD_QW1_L2TAG1_SHIFT)
559 
560 /* Context descriptors */
561 struct iavf_tx_context_desc {
562 	__le32 tunneling_params;
563 	__le16 l2tag2;
564 	__le16 rsvd;
565 	__le64 type_cmd_tso_mss;
566 };
567 
568 #define IAVF_TXD_CTX_QW1_CMD_SHIFT	4
569 #define IAVF_TXD_CTX_QW1_CMD_MASK	(0xFFFFUL << IAVF_TXD_CTX_QW1_CMD_SHIFT)
570 
571 enum iavf_tx_ctx_desc_cmd_bits {
572 	IAVF_TX_CTX_DESC_TSO		= 0x01,
573 	IAVF_TX_CTX_DESC_TSYN		= 0x02,
574 	IAVF_TX_CTX_DESC_IL2TAG2	= 0x04,
575 	IAVF_TX_CTX_DESC_IL2TAG2_IL2H	= 0x08,
576 	IAVF_TX_CTX_DESC_SWTCH_NOTAG	= 0x00,
577 	IAVF_TX_CTX_DESC_SWTCH_UPLINK	= 0x10,
578 	IAVF_TX_CTX_DESC_SWTCH_LOCAL	= 0x20,
579 	IAVF_TX_CTX_DESC_SWTCH_VSI	= 0x30,
580 	IAVF_TX_CTX_DESC_SWPE		= 0x40
581 };
582 
583 /* Packet Classifier Types for filters */
584 enum iavf_filter_pctype {
585 	/* Note: Values 0-28 are reserved for future use.
586 	 * Value 29, 30, 32 are not supported on XL710 and X710.
587 	 */
588 	IAVF_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP	= 29,
589 	IAVF_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP	= 30,
590 	IAVF_FILTER_PCTYPE_NONF_IPV4_UDP		= 31,
591 	IAVF_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK	= 32,
592 	IAVF_FILTER_PCTYPE_NONF_IPV4_TCP		= 33,
593 	IAVF_FILTER_PCTYPE_NONF_IPV4_SCTP		= 34,
594 	IAVF_FILTER_PCTYPE_NONF_IPV4_OTHER		= 35,
595 	IAVF_FILTER_PCTYPE_FRAG_IPV4			= 36,
596 	/* Note: Values 37-38 are reserved for future use.
597 	 * Value 39, 40, 42 are not supported on XL710 and X710.
598 	 */
599 	IAVF_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP	= 39,
600 	IAVF_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP	= 40,
601 	IAVF_FILTER_PCTYPE_NONF_IPV6_UDP		= 41,
602 	IAVF_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK	= 42,
603 	IAVF_FILTER_PCTYPE_NONF_IPV6_TCP		= 43,
604 	IAVF_FILTER_PCTYPE_NONF_IPV6_SCTP		= 44,
605 	IAVF_FILTER_PCTYPE_NONF_IPV6_OTHER		= 45,
606 	IAVF_FILTER_PCTYPE_FRAG_IPV6			= 46,
607 	/* Note: Value 47 is reserved for future use */
608 	IAVF_FILTER_PCTYPE_FCOE_OX			= 48,
609 	IAVF_FILTER_PCTYPE_FCOE_RX			= 49,
610 	IAVF_FILTER_PCTYPE_FCOE_OTHER			= 50,
611 	/* Note: Values 51-62 are reserved for future use */
612 	IAVF_FILTER_PCTYPE_L2_PAYLOAD			= 63,
613 };
614 
615 #define IAVF_TXD_CTX_QW1_TSO_LEN_SHIFT	30
616 #define IAVF_TXD_CTX_QW1_TSO_LEN_MASK	(0x3FFFFULL << \
617 					 IAVF_TXD_CTX_QW1_TSO_LEN_SHIFT)
618 
619 #define IAVF_TXD_CTX_QW1_MSS_SHIFT	50
620 #define IAVF_TXD_CTX_QW1_MSS_MASK	(0x3FFFULL << \
621 					 IAVF_TXD_CTX_QW1_MSS_SHIFT)
622 
623 #define IAVF_TXD_CTX_QW1_VSI_SHIFT	50
624 #define IAVF_TXD_CTX_QW1_VSI_MASK	(0x1FFULL << IAVF_TXD_CTX_QW1_VSI_SHIFT)
625 
626 #define IAVF_TXD_CTX_QW0_EXT_IP_SHIFT	0
627 #define IAVF_TXD_CTX_QW0_EXT_IP_MASK	(0x3ULL << \
628 					 IAVF_TXD_CTX_QW0_EXT_IP_SHIFT)
629 
630 enum iavf_tx_ctx_desc_eipt_offload {
631 	IAVF_TX_CTX_EXT_IP_NONE		= 0x0,
632 	IAVF_TX_CTX_EXT_IP_IPV6		= 0x1,
633 	IAVF_TX_CTX_EXT_IP_IPV4_NO_CSUM	= 0x2,
634 	IAVF_TX_CTX_EXT_IP_IPV4		= 0x3
635 };
636 
637 #define IAVF_TXD_CTX_QW0_EXT_IPLEN_SHIFT	2
638 #define IAVF_TXD_CTX_QW0_EXT_IPLEN_MASK	(0x3FULL << \
639 					 IAVF_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
640 
641 #define IAVF_TXD_CTX_QW0_NATT_SHIFT	9
642 #define IAVF_TXD_CTX_QW0_NATT_MASK	(0x3ULL << IAVF_TXD_CTX_QW0_NATT_SHIFT)
643 
644 #define IAVF_TXD_CTX_UDP_TUNNELING	BIT_ULL(IAVF_TXD_CTX_QW0_NATT_SHIFT)
645 #define IAVF_TXD_CTX_GRE_TUNNELING	(0x2ULL << IAVF_TXD_CTX_QW0_NATT_SHIFT)
646 
647 #define IAVF_TXD_CTX_QW0_EIP_NOINC_SHIFT	11
648 #define IAVF_TXD_CTX_QW0_EIP_NOINC_MASK \
649 				       BIT_ULL(IAVF_TXD_CTX_QW0_EIP_NOINC_SHIFT)
650 
651 #define IAVF_TXD_CTX_EIP_NOINC_IPID_CONST	IAVF_TXD_CTX_QW0_EIP_NOINC_MASK
652 
653 #define IAVF_TXD_CTX_QW0_NATLEN_SHIFT	12
654 #define IAVF_TXD_CTX_QW0_NATLEN_MASK	(0X7FULL << \
655 					 IAVF_TXD_CTX_QW0_NATLEN_SHIFT)
656 
657 #define IAVF_TXD_CTX_QW0_DECTTL_SHIFT	19
658 #define IAVF_TXD_CTX_QW0_DECTTL_MASK	(0xFULL << \
659 					 IAVF_TXD_CTX_QW0_DECTTL_SHIFT)
660 
661 #define IAVF_TXD_CTX_QW0_L4T_CS_SHIFT	23
662 #define IAVF_TXD_CTX_QW0_L4T_CS_MASK	BIT_ULL(IAVF_TXD_CTX_QW0_L4T_CS_SHIFT)
663 
664 /* Statistics collected by each port, VSI, VEB, and S-channel */
665 struct iavf_eth_stats {
666 	u64 rx_bytes;			/* gorc */
667 	u64 rx_unicast;			/* uprc */
668 	u64 rx_multicast;		/* mprc */
669 	u64 rx_broadcast;		/* bprc */
670 	u64 rx_discards;		/* rdpc */
671 	u64 rx_unknown_protocol;	/* rupp */
672 	u64 tx_bytes;			/* gotc */
673 	u64 tx_unicast;			/* uptc */
674 	u64 tx_multicast;		/* mptc */
675 	u64 tx_broadcast;		/* bptc */
676 	u64 tx_discards;		/* tdpc */
677 	u64 tx_errors;			/* tepc */
678 };
679 #endif /* _IAVF_TYPE_H_ */
680