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Searched refs:HWADDR_PRIX (Results 1 – 17 of 17) sorted by relevance

/openbmc/qemu/hw/m68k/
H A Dmcf5208.c123 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n", in m5208_timer_write()
149 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n", in m5208_timer_read()
179 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n", in m5208_sys_read()
188 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n", in m5208_sys_write()
218 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n", in m5208_rcm_write()
H A Dmcf5206.c406 qemu_log_mask(LOG_GUEST_ERROR, "Bad MBAR read offset 0x%" HWADDR_PRIX, in m5206_mbar_readb()
427 qemu_log_mask(LOG_GUEST_ERROR, "Bad MBAR read offset 0x%" HWADDR_PRIX, in m5206_mbar_readw()
453 qemu_log_mask(LOG_GUEST_ERROR, "Bad MBAR read offset 0x%" HWADDR_PRIX, in m5206_mbar_readl()
479 qemu_log_mask(LOG_GUEST_ERROR, "Bad MBAR write offset 0x%" HWADDR_PRIX, in m5206_mbar_writeb()
505 qemu_log_mask(LOG_GUEST_ERROR, "Bad MBAR write offset 0x%" HWADDR_PRIX, in m5206_mbar_writew()
535 qemu_log_mask(LOG_GUEST_ERROR, "Bad MBAR write offset 0x%" HWADDR_PRIX, in m5206_mbar_writel()
/openbmc/qemu/hw/arm/
H A Dintegratorcp.c151 "%s: Unimplemented offset 0x%" HWADDR_PRIX "\n", in integratorcm_read()
260 "%s: Unimplemented offset 0x%" HWADDR_PRIX "\n", in integratorcm_write()
398 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n", in icp_pic_read()
435 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n", in icp_pic_write()
509 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n", in icp_control_read()
530 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n", in icp_control_write()
/openbmc/qemu/hw/intc/
H A Drx_icu.c180 HWADDR_PRIX "\n", in icu_read()
212 qemu_log_mask(LOG_UNIMP, "rx_icu: Register 0x%" HWADDR_PRIX " " in icu_read()
228 "0x%" HWADDR_PRIX "\n", in icu_write()
279 qemu_log_mask(LOG_UNIMP, "rx_icu: Register 0x%" HWADDR_PRIX " " in icu_write()
/openbmc/qemu/hw/display/
H A Ddpcd.c60 qemu_log_mask(LOG_GUEST_ERROR, "dpcd: Bad offset 0x%" HWADDR_PRIX "\n", in dpcd_read()
78 qemu_log_mask(LOG_GUEST_ERROR, "dpcd: Bad offset 0x%" HWADDR_PRIX "\n", in dpcd_write()
H A Dxlnx_dp.c928 DPRINTF("vblend: write @0x%" HWADDR_PRIX " = 0x%" PRIX32 "\n", offset, in xlnx_dp_vblend_write()
1015 DPRINTF("vblend: read @0x%" HWADDR_PRIX " = 0x%" PRIX32 "\n", offset, in xlnx_dp_vblend_read()
1042 DPRINTF("avbufm: write @0x%" HWADDR_PRIX " = 0x%" PRIX32 "\n", offset, in xlnx_dp_avbufm_write()
/openbmc/qemu/hw/dma/
H A Dsifive_pdma.c206 "%s: Unexpected 64-bit access to 0x%" HWADDR_PRIX "\n", in sifive_pdma_readq()
267 "%s: Unexpected 32-bit access to 0x%" HWADDR_PRIX "\n", in sifive_pdma_readl()
324 "%s: Unexpected 64-bit access to 0x%" HWADDR_PRIX "\n", in sifive_pdma_writeq()
407 "%s: Unexpected 32-bit access to 0x%" HWADDR_PRIX "\n", in sifive_pdma_writel()
/openbmc/qemu/include/exec/
H A Dhwaddr.h19 #define HWADDR_PRIX PRIX64 macro
/openbmc/qemu/hw/timer/
H A Drenesas_tmr.c201 HWADDR_PRIX "\n", in tmr_read()
255 qemu_log_mask(LOG_UNIMP, "renesas_tmr: Register 0x%" HWADDR_PRIX in tmr_read()
284 "renesas_tmr: Invalid write size 0x%" HWADDR_PRIX "\n", in tmr_write()
308 qemu_log_mask(LOG_UNIMP, "renesas_tmr: Register 0x%" HWADDR_PRIX in tmr_write()
H A Drenesas_cmt.c123 qemu_log_mask(LOG_UNIMP, "renesas_cmt: Register 0x%" HWADDR_PRIX " " in cmt_read()
166 qemu_log_mask(LOG_UNIMP, "renesas_cmt: Register 0x%" HWADDR_PRIX " " in cmt_write()
H A Dexynos4210_mct.c1162 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n", in exynos4210_mct_read()
1488 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n", in exynos4210_mct_write()
/openbmc/qemu/hw/char/
H A Drenesas_sci.c204 qemu_log_mask(LOG_UNIMP, "renesas_sci: Register 0x%" HWADDR_PRIX " " in sci_write()
234 qemu_log_mask(LOG_UNIMP, "renesas_sci: Register 0x%" HWADDR_PRIX in sci_read()
/openbmc/qemu/hw/net/
H A Dmcf_fec.c394 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address 0x%" HWADDR_PRIX "\n", in mcf_fec_read()
495 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address 0x%" HWADDR_PRIX "\n", in mcf_fec_write()
/openbmc/qemu/hw/mips/
H A Dmalta.c448 "malta_fpga_read: Bad register addr 0x%"HWADDR_PRIX"\n", in malta_fpga_read()
535 "malta_fpga_write: Bad register addr 0x%"HWADDR_PRIX"\n", in malta_fpga_write()
/openbmc/qemu/system/
H A Dmemory.c555 "%s at addr: 0x%" HWADDR_PRIX, in access_with_adjusted_size_aligned()
1542 qemu_log_mask(LOG_GUEST_ERROR, "Invalid %s at addr 0x%" HWADDR_PRIX in memory_region_access_valid()
1550 qemu_log_mask(LOG_GUEST_ERROR, "Invalid %s at addr 0x%" HWADDR_PRIX in memory_region_access_valid()
1564 qemu_log_mask(LOG_GUEST_ERROR, "Invalid %s at addr 0x%" HWADDR_PRIX in memory_region_access_valid()
H A Dphysmem.c2756 "addr 0x%" HWADDR_PRIX ", size %" HWADDR_PRIu ", " in flatview_access_allowed()
/openbmc/qemu/hw/ide/
H A Dahci.c479 "ahci: Mis-aligned write to addr 0x%03" HWADDR_PRIX "\n", in ahci_mem_write()