xref: /openbmc/linux/drivers/net/ethernet/ti/cpts.h (revision b78aba49)
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * TI Common Platform Time Sync
4  *
5  * Copyright (C) 2012 Richard Cochran <richardcochran@gmail.com>
6  *
7  */
8 #ifndef _TI_CPTS_H_
9 #define _TI_CPTS_H_
10 
11 #if IS_ENABLED(CONFIG_TI_CPTS)
12 
13 #include <linux/clk.h>
14 #include <linux/clkdev.h>
15 #include <linux/clocksource.h>
16 #include <linux/device.h>
17 #include <linux/list.h>
18 #include <linux/of.h>
19 #include <linux/ptp_clock_kernel.h>
20 #include <linux/skbuff.h>
21 #include <linux/ptp_classify.h>
22 #include <linux/timecounter.h>
23 
24 struct cpsw_cpts {
25 	u32 idver;                /* Identification and version */
26 	u32 control;              /* Time sync control */
27 	u32 rftclk_sel;		  /* Reference Clock Select Register */
28 	u32 ts_push;              /* Time stamp event push */
29 	u32 ts_load_val;          /* Time stamp load value */
30 	u32 ts_load_en;           /* Time stamp load enable */
31 	u32 res2[2];
32 	u32 intstat_raw;          /* Time sync interrupt status raw */
33 	u32 intstat_masked;       /* Time sync interrupt status masked */
34 	u32 int_enable;           /* Time sync interrupt enable */
35 	u32 res3;
36 	u32 event_pop;            /* Event interrupt pop */
37 	u32 event_low;            /* 32 Bit Event Time Stamp */
38 	u32 event_high;           /* Event Type Fields */
39 };
40 
41 /* Bit definitions for the IDVER register */
42 #define TX_IDENT_SHIFT       (16)    /* TX Identification Value */
43 #define TX_IDENT_MASK        (0xffff)
44 #define RTL_VER_SHIFT        (11)    /* RTL Version Value */
45 #define RTL_VER_MASK         (0x1f)
46 #define MAJOR_VER_SHIFT      (8)     /* Major Version Value */
47 #define MAJOR_VER_MASK       (0x7)
48 #define MINOR_VER_SHIFT      (0)     /* Minor Version Value */
49 #define MINOR_VER_MASK       (0xff)
50 
51 /* Bit definitions for the CONTROL register */
52 #define HW4_TS_PUSH_EN       (1<<11) /* Hardware push 4 enable */
53 #define HW3_TS_PUSH_EN       (1<<10) /* Hardware push 3 enable */
54 #define HW2_TS_PUSH_EN       (1<<9)  /* Hardware push 2 enable */
55 #define HW1_TS_PUSH_EN       (1<<8)  /* Hardware push 1 enable */
56 #define INT_TEST             (1<<1)  /* Interrupt Test */
57 #define CPTS_EN              (1<<0)  /* Time Sync Enable */
58 
59 /*
60  * Definitions for the single bit resisters:
61  * TS_PUSH TS_LOAD_EN  INTSTAT_RAW INTSTAT_MASKED INT_ENABLE EVENT_POP
62  */
63 #define TS_PUSH             (1<<0)  /* Time stamp event push */
64 #define TS_LOAD_EN          (1<<0)  /* Time Stamp Load */
65 #define TS_PEND_RAW         (1<<0)  /* int read (before enable) */
66 #define TS_PEND             (1<<0)  /* masked interrupt read (after enable) */
67 #define TS_PEND_EN          (1<<0)  /* masked interrupt enable */
68 #define EVENT_POP           (1<<0)  /* writing discards one event */
69 
70 /* Bit definitions for the EVENT_HIGH register */
71 #define PORT_NUMBER_SHIFT    (24)    /* Indicates Ethernet port or HW pin */
72 #define PORT_NUMBER_MASK     (0x1f)
73 #define EVENT_TYPE_SHIFT     (20)    /* Time sync event type */
74 #define EVENT_TYPE_MASK      (0xf)
75 #define MESSAGE_TYPE_SHIFT   (16)    /* PTP message type */
76 #define MESSAGE_TYPE_MASK    (0xf)
77 #define SEQUENCE_ID_SHIFT    (0)     /* PTP message sequence ID */
78 #define SEQUENCE_ID_MASK     (0xffff)
79 
80 enum {
81 	CPTS_EV_PUSH, /* Time Stamp Push Event */
82 	CPTS_EV_ROLL, /* Time Stamp Rollover Event */
83 	CPTS_EV_HALF, /* Time Stamp Half Rollover Event */
84 	CPTS_EV_HW,   /* Hardware Time Stamp Push Event */
85 	CPTS_EV_RX,   /* Ethernet Receive Event */
86 	CPTS_EV_TX,   /* Ethernet Transmit Event */
87 };
88 
89 #define CPTS_FIFO_DEPTH 16
90 #define CPTS_MAX_EVENTS 32
91 
92 struct cpts_event {
93 	struct list_head list;
94 	unsigned long tmo;
95 	u32 high;
96 	u32 low;
97 	u64 timestamp;
98 };
99 
100 struct cpts {
101 	struct device *dev;
102 	struct cpsw_cpts __iomem *reg;
103 	int tx_enable;
104 	int rx_enable;
105 	struct ptp_clock_info info;
106 	struct ptp_clock *clock;
107 	spinlock_t lock; /* protects fifo/events */
108 	u32 cc_mult; /* for the nominal frequency */
109 	struct cyclecounter cc;
110 	struct timecounter tc;
111 	int phc_index;
112 	struct clk *refclk;
113 	struct list_head events;
114 	struct list_head pool;
115 	struct cpts_event pool_data[CPTS_MAX_EVENTS];
116 	unsigned long ov_check_period;
117 	struct sk_buff_head txq;
118 	u64 cur_timestamp;
119 	u32 mult_new;
120 	struct mutex ptp_clk_mutex; /* sync PTP interface and worker */
121 	bool irq_poll;
122 	struct completion	ts_push_complete;
123 	u32 hw_ts_enable;
124 };
125 
126 void cpts_rx_timestamp(struct cpts *cpts, struct sk_buff *skb);
127 void cpts_tx_timestamp(struct cpts *cpts, struct sk_buff *skb);
128 int cpts_register(struct cpts *cpts);
129 void cpts_unregister(struct cpts *cpts);
130 struct cpts *cpts_create(struct device *dev, void __iomem *regs,
131 			 struct device_node *node, u32 n_ext_ts);
132 void cpts_release(struct cpts *cpts);
133 void cpts_misc_interrupt(struct cpts *cpts);
134 
cpts_can_timestamp(struct cpts * cpts,struct sk_buff * skb)135 static inline bool cpts_can_timestamp(struct cpts *cpts, struct sk_buff *skb)
136 {
137 	unsigned int class = ptp_classify_raw(skb);
138 
139 	if (class == PTP_CLASS_NONE)
140 		return false;
141 
142 	return true;
143 }
144 
cpts_set_irqpoll(struct cpts * cpts,bool en)145 static inline void cpts_set_irqpoll(struct cpts *cpts, bool en)
146 {
147 	cpts->irq_poll = en;
148 }
149 
150 #else
151 struct cpts;
152 
cpts_rx_timestamp(struct cpts * cpts,struct sk_buff * skb)153 static inline void cpts_rx_timestamp(struct cpts *cpts, struct sk_buff *skb)
154 {
155 }
cpts_tx_timestamp(struct cpts * cpts,struct sk_buff * skb)156 static inline void cpts_tx_timestamp(struct cpts *cpts, struct sk_buff *skb)
157 {
158 }
159 
160 static inline
cpts_create(struct device * dev,void __iomem * regs,struct device_node * node,u32 n_ext_ts)161 struct cpts *cpts_create(struct device *dev, void __iomem *regs,
162 			 struct device_node *node, u32 n_ext_ts)
163 {
164 	return NULL;
165 }
166 
cpts_release(struct cpts * cpts)167 static inline void cpts_release(struct cpts *cpts)
168 {
169 }
170 
171 static inline int
cpts_register(struct cpts * cpts)172 cpts_register(struct cpts *cpts)
173 {
174 	return 0;
175 }
176 
cpts_unregister(struct cpts * cpts)177 static inline void cpts_unregister(struct cpts *cpts)
178 {
179 }
180 
cpts_can_timestamp(struct cpts * cpts,struct sk_buff * skb)181 static inline bool cpts_can_timestamp(struct cpts *cpts, struct sk_buff *skb)
182 {
183 	return false;
184 }
185 
cpts_misc_interrupt(struct cpts * cpts)186 static inline void cpts_misc_interrupt(struct cpts *cpts)
187 {
188 }
189 
cpts_set_irqpoll(struct cpts * cpts,bool en)190 static inline void cpts_set_irqpoll(struct cpts *cpts, bool en)
191 {
192 }
193 #endif
194 
195 
196 #endif
197