Searched refs:HPLL (Results 1 – 7 of 7) sorted by relevance
| /openbmc/u-boot/arch/arm/mach-s5pc1xx/include/mach/ |
| H A D | clk.h | 14 #define HPLL 3 macro
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| /openbmc/u-boot/arch/arm/mach-exynos/include/mach/ |
| H A D | clk.h | 13 #define HPLL 3 macro
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| /openbmc/linux/Documentation/devicetree/bindings/clock/ |
| H A D | qcom,hfpll.txt | 19 Definition: address and size of HPLL registers. An optional second
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| /openbmc/u-boot/board/samsung/smdkc100/ |
| H A D | lowlevel_init.S | 104 ldr r1, =0x1111 @ A, M, E, HPLL Muxing
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| /openbmc/u-boot/arch/arm/mach-s5pc1xx/ |
| H A D | clock.c | 42 case HPLL: in s5pc100_get_pll_clk()
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| /openbmc/u-boot/board/samsung/goni/ |
| H A D | lowlevel_init.S | 284 ldr r1, =0x00001111 @ A, M, E, HPLL Muxing
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| /openbmc/u-boot/arch/arm/mach-aspeed/ast2500/ |
| H A D | platform.S | 725 ldr r0, =0x1e6e2160 @ set 24M Jitter divider (HPLL=825MHz)
2475 mov r2, #0x04 @ Default RMII, set MHCLK = HPLL/10
2477 movne r2, #0x02 @ if RGMII, set MHCLK = HPLL/6
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