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Searched refs:HHI_MPLL3_CNTL0 (Results 1 – 5 of 5) sorted by relevance

/openbmc/u-boot/arch/arm/include/asm/arch-meson/
H A Dclock-axg.h90 #define HHI_MPLL3_CNTL0 0x2E0 macro
H A Dclock-gx.h85 #define HHI_MPLL3_CNTL0 0x2E0 /* 0xb8 offset in data sheet */ macro
/openbmc/linux/drivers/clk/meson/
H A Daxg.h91 #define HHI_MPLL3_CNTL0 0x2E0 macro
H A Dgxbb.h85 #define HHI_MPLL3_CNTL0 0x2E0 /* 0xb8 offset in data sheet */ macro
H A Daxg.c648 .reg_off = HHI_MPLL3_CNTL0,
653 .reg_off = HHI_MPLL3_CNTL0,
658 .reg_off = HHI_MPLL3_CNTL0,
682 .offset = HHI_MPLL3_CNTL0,