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Searched refs:HHI_HDMI_PLL_CNTL4 (Results 1 – 5 of 5) sorted by relevance

/openbmc/linux/drivers/gpu/drm/meson/
H A Dmeson_vclk.c103 #define HHI_HDMI_PLL_CNTL4 0x32C /* 0xcb offset in data sheet */ macro
249 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x801da72c); in meson_venci_cvbs_clock_config()
262 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x0c4d000c); in meson_venci_cvbs_clock_config()
279 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x6a28dc00); in meson_venci_cvbs_clock_config()
505 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x801da72c); in meson_hdmi_pll_set_params()
521 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x0c8e0000); in meson_hdmi_pll_set_params()
548 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, in meson_hdmi_pll_set_params()
553 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, in meson_hdmi_pll_set_params()
561 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x0a691c00); in meson_hdmi_pll_set_params()
/openbmc/u-boot/drivers/video/meson/
H A Dmeson_vclk.c73 #define HHI_HDMI_PLL_CNTL4 0x32C /* 0xcb offset in data sheet */ macro
216 hhi_write(HHI_HDMI_PLL_CNTL4, 0x801da72c); in meson_venci_cvbs_clock_config()
225 hhi_write(HHI_HDMI_PLL_CNTL4, 0x0c4d000c); in meson_venci_cvbs_clock_config()
405 hhi_write(HHI_HDMI_PLL_CNTL4, 0x801da72c); in meson_hdmi_pll_set_params()
421 hhi_write(HHI_HDMI_PLL_CNTL4, 0x0c8e0000); in meson_hdmi_pll_set_params()
/openbmc/linux/drivers/clk/meson/
H A Dgxbb.h100 #define HHI_HDMI_PLL_CNTL4 0x32C /* 0xcb offset in data sheet */ macro
H A Dg12a.h117 #define HHI_HDMI_PLL_CNTL4 0x330 macro
/openbmc/u-boot/arch/arm/include/asm/arch-meson/
H A Dclock-gx.h100 #define HHI_HDMI_PLL_CNTL4 0x32C /* 0xcb offset in data sheet */ macro