Searched refs:HHI_HDMI_PHY_CNTL1 (Results 1 – 5 of 5) sorted by relevance
| /openbmc/linux/drivers/phy/amlogic/ |
| H A D | phy-meson8-hdmi-tx.c | 29 #define HHI_HDMI_PHY_CNTL1 0x3a4 macro
71 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL1, 0x0); in phy_meson8_hdmi_tx_power_on()
75 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL1, in phy_meson8_hdmi_tx_power_on()
80 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL1, in phy_meson8_hdmi_tx_power_on()
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| /openbmc/u-boot/drivers/video/meson/ |
| H A D | meson_dw_hdmi.c | 37 #define HHI_HDMI_PHY_CNTL1 0x3a4 /* 0xe9 */ macro
206 dw_hdmi_hhi_update_bits(priv, HHI_HDMI_PHY_CNTL1, 0xf, 0xf); in meson_dw_hdmi_phy_reset()
211 dw_hdmi_hhi_update_bits(priv, HHI_HDMI_PHY_CNTL1, 0xf, 0xe); in meson_dw_hdmi_phy_reset()
290 dw_hdmi_hhi_update_bits(priv, HHI_HDMI_PHY_CNTL1, in meson_dw_hdmi_phy_init()
296 dw_hdmi_hhi_update_bits(priv, HHI_HDMI_PHY_CNTL1, BIT(17), 0); in meson_dw_hdmi_phy_init()
298 dw_hdmi_hhi_update_bits(priv, HHI_HDMI_PHY_CNTL1, in meson_dw_hdmi_phy_init()
302 dw_hdmi_hhi_update_bits(priv, HHI_HDMI_PHY_CNTL1, 0xf, 0); in meson_dw_hdmi_phy_init()
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| /openbmc/linux/drivers/gpu/drm/meson/ |
| H A D | meson_dw_hdmi.c | 108 #define HHI_HDMI_PHY_CNTL1 0x3a4 /* 0xe9 */ macro
362 regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1, 0xf, 0xf); in meson_dw_hdmi_phy_reset()
367 regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1, 0xf, 0xe); in meson_dw_hdmi_phy_reset()
413 regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1, 0xf, 0); in dw_hdmi_phy_init()
466 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL1, dw_hdmi->data->cntl1_init); in dw_hdmi_phy_disable()
648 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL1, meson_dw_hdmi->data->cntl1_init); in meson_dw_hdmi_init()
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| /openbmc/linux/drivers/clk/meson/ |
| H A D | gxbb.h | 107 #define HHI_HDMI_PHY_CNTL1 0x3A4 /* 0xe9 offset in data sheet */ macro
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| /openbmc/u-boot/arch/arm/include/asm/arch-meson/ |
| H A D | clock-gx.h | 107 #define HHI_HDMI_PHY_CNTL1 0x3A4 /* 0xe9 offset in data sheet */ macro
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