Searched refs:HDMI_NV_PDISP_SOR_PLL0 (Results 1 – 2 of 2) sorted by relevance
837 tegra_hdmi_writel(hdmi, tmds->pll0, HDMI_NV_PDISP_SOR_PLL0); in tegra_hdmi_setup_tmds()979 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PLL0),1246 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PLL0); in tegra_hdmi_encoder_enable()1248 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_PLL0); in tegra_hdmi_encoder_enable()1252 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PLL0); in tegra_hdmi_encoder_enable()1254 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_PLL0); in tegra_hdmi_encoder_enable()
165 #define HDMI_NV_PDISP_SOR_PLL0 0x57 macro