Searched refs:HCLK_SDIO0 (Results 1 – 13 of 13) sorted by relevance
| /openbmc/u-boot/drivers/clk/rockchip/ |
| H A D | clk_rk3288.c | 590 case HCLK_SDIO0: in rockchip_mmc_get_clk()
640 case HCLK_SDIO0: in rockchip_mmc_set_clk()
755 case HCLK_SDIO0: in rk3288_clk_get_rate()
805 case HCLK_SDIO0: in rk3288_clk_set_rate()
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| /openbmc/u-boot/include/dt-bindings/clock/ |
| H A D | rk3288-cru.h | 167 #define HCLK_SDIO0 457 macro
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| H A D | rk3368-cru.h | 164 #define HCLK_SDIO0 457 macro
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| /openbmc/linux/include/dt-bindings/clock/ |
| H A D | rk3288-cru.h | 175 #define HCLK_SDIO0 457 macro
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| H A D | rk3368-cru.h | 164 #define HCLK_SDIO0 457 macro
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| /openbmc/linux/drivers/clk/rockchip/ |
| H A D | clk-rk3368.c | 787 GATE(HCLK_SDIO0, "hclk_sdio0", "hclk_peri", 0, RK3368_CLKGATE_CON(21), 1, GFLAGS),
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| H A D | clk-rk3288.c | 727 GATE(HCLK_SDIO0, "hclk_sdio0", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 4, GFLAGS),
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| /openbmc/u-boot/arch/arm/dts/ |
| H A D | rk3288-veyron.dtsi | 275 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>, <&cru SCLK_SDIO0_DRV>,
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| H A D | rk3368.dtsi | 262 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
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| H A D | rk3288.dtsi | 181 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
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| /openbmc/linux/drivers/clk/renesas/ |
| H A D | r9a06g032-clocks.c | 568 D_MODULE(HCLK_SDIO0, "hclk_sdio0", CLK_REF_SYNC_D4, RB(0x0c, 0),
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| /openbmc/linux/arch/arm64/boot/dts/rockchip/ |
| H A D | rk3368.dtsi | 197 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
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| /openbmc/linux/arch/arm/boot/dts/rockchip/ |
| H A D | rk3288.dtsi | 225 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
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