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Searched refs:GPIO_CNTL (Results 1 – 4 of 4) sorted by relevance

/openbmc/u-boot/arch/x86/include/asm/arch-ivybridge/
H A Dpch.h73 #define GPIO_CNTL 0x4C /* LPC GPIO Control Register */ macro
96 #define GPIO_CNTL 0x4C /* LPC GPIO Control Register */ macro
/openbmc/u-boot/arch/x86/include/asm/arch-broadwell/
H A Dpch.h17 #define GPIO_CNTL 0x4C /* LPC GPIO Control Register */ macro
/openbmc/u-boot/arch/x86/cpu/ivybridge/
H A Dlpc.c497 dm_pci_write_config32(dev->parent, GPIO_CNTL, 0x10); in bd82x6x_lpc_early_init()
/openbmc/u-boot/arch/x86/cpu/broadwell/
H A Dpch.c48 dm_pci_write_config8(dev, GPIO_CNTL, GPIO_EN); in broadwell_pch_early_init()