| /openbmc/qemu/tests/qtest/ |
| H A D | npcm7xx_gpio-test.c | 21 #define GPIO(x) (0xf0010000 + (x) * 0x1000) macro
58 if (readl(GPIO(n) + GP_N_TLOCK1) != 0) { in gpio_unlock()
59 writel(GPIO(n) + GP_N_TLOCK2, 0xc0de1248); in gpio_unlock()
60 writel(GPIO(n) + GP_N_TLOCK1, 0xc0defa73); in gpio_unlock()
69 writel(GPIO(n) + GP_N_EVEN, 0x00000000); in gpio_reset()
70 writel(GPIO(n) + GP_N_EVST, 0xffffffff); in gpio_reset()
71 writel(GPIO(n) + GP_N_POL, 0x00000000); in gpio_reset()
72 writel(GPIO(n) + GP_N_DOUT, 0x00000000); in gpio_reset()
73 writel(GPIO(n) + GP_N_OE, 0x00000000); in gpio_reset()
74 writel(GPIO(n) + GP_N_OTYP, 0x00000000); in gpio_reset()
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| /openbmc/witherspoon-pfault-analysis/ |
| H A D | gpio.hpp | 46 class GPIO class
49 GPIO() = delete;
50 GPIO(const GPIO&) = delete;
51 GPIO(GPIO&&) = default;
52 GPIO& operator=(const GPIO&) = delete;
53 GPIO& operator=(GPIO&&) = default;
54 ~GPIO() = default;
63 GPIO(const std::string& device, gpioNum_t gpio, Direction direction) : in GPIO() function in witherspoon::gpio::GPIO
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| /openbmc/phosphor-power/ |
| H A D | gpio.hpp | 46 class GPIO class
49 GPIO() = delete;
50 GPIO(const GPIO&) = delete;
51 GPIO(GPIO&&) = default;
52 GPIO& operator=(const GPIO&) = delete;
53 GPIO& operator=(GPIO&&) = default;
54 ~GPIO() = default;
63 GPIO(const std::string& device, gpioNum_t gpio, Direction direction) : in GPIO() function in phosphor::gpio::GPIO
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| /openbmc/phosphor-power/phosphor-power-sequencer/src/ |
| H A D | gpio.hpp | 30 class GPIO class
33 GPIO() = default;
34 GPIO(const GPIO&) = delete;
35 GPIO(GPIO&&) = delete;
36 GPIO& operator=(const GPIO&) = delete;
37 GPIO& operator=(GPIO&&) = delete;
38 virtual ~GPIO() = default;
91 class BMCGPIO : public GPIO
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| /openbmc/openbmc/meta-facebook/meta-tiogapass/recipes-phosphor/flash/phosphor-software-manager/ |
| H A D | bios-update | 7 GPIO=389
21 if [ ! -d /sys/class/gpio/gpio$GPIO ]; then
23 echo $GPIO > "export"
24 cd gpio$GPIO
26 cd /sys/class/gpio/gpio$GPIO
42 if [ ! -d /sys/class/gpio/gpio$GPIO ]; then
44 echo $GPIO > "export"
45 cd gpio$GPIO
47 cd /sys/class/gpio/gpio$GPIO
58 echo $GPIO > /sys/class/gpio/unexport
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| /openbmc/u-boot/drivers/gpio/ |
| H A D | Kconfig | 2 # GPIO infrastructure and drivers
5 menu "GPIO Support"
8 bool "Enable Driver Model for GPIO drivers"
11 Enable driver model for GPIO access. The standard GPIO
13 the GPIO uclass. Drivers provide methods to query the
18 bool "Enable GPIO hog support"
23 The GPIO chip may contain GPIO hog definitions. GPIO hogging
24 is a mechanism providing automatic GPIO request and config-
28 bool "Enable GPIO hog support in SPL"
33 The GPIO chip may contain GPIO hog definitions. GPIO hogging
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| /openbmc/skeleton/libopenbmc_intf/ |
| H A D | gpio.h | 16 } GPIO; typedef
28 void gpio_close(GPIO*);
29 int gpio_open(GPIO*, uint8_t);
30 int gpio_write(GPIO*, uint8_t);
31 int gpio_get_params(GPIO*);
32 int gpio_read(GPIO*,uint8_t*);
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| H A D | gpio_configs.h | 27 GPIO latch_out; /* NULL name if not used. */
29 GPIO power_good_in;
32 GPIO *power_up_outs;
37 GPIO *reset_outs;
41 GPIO *pci_reset_outs;
|
| H A D | GPIOS.md | 1 # GPIO JSON format
3 GPIO definitions are stored in '/etc/default/obmc/gpio/gpio_defs.json' on the
47 This section contains The GPIO pins and directions.
59 #The GPIO pin.
63 #raw number the GPIO would be accessed with.
66 #The GPIO direction - in, out, rising, falling, or both
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| /openbmc/phosphor-power/phosphor-power-sequencer/docs/ |
| H A D | named_gpios.md | 6 toggling a named GPIO to the power sequencer device in the chassis.
8 The GPIO name is defined in the Linux device tree. For single chassis systems,
9 the standard GPIO name is `power-chassis-control`. See
10 [Device Tree GPIO Naming in OpenBMC](https://github.com/openbmc/docs/blob/master/designs/device-tre…
13 The GPIO name in each chassis is specified in the
15 found for the current system, the standard GPIO name is used.
23 from a named GPIO.
25 The GPIO name is defined in the Linux device tree. For single chassis systems,
26 the standard GPIO name is `power-chassis-good`. See
27 [Device Tree GPIO Naming in OpenBMC](https://github.com/openbmc/docs/blob/master/designs/device-tre…
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| /openbmc/u-boot/doc/device-tree-bindings/gpio/ |
| H A D | gpio.txt | 1 Specifying GPIO information for devices
16 GPIO properties should be named "[<name>-]gpios", with <name> being the purpose
17 of this GPIO for the device. While a non-existent <name> is considered valid
21 GPIO properties can contain one or more GPIO phandles, but only in exceptional
30 The following example could be used to describe GPIO pins used as device enable
66 GPIO pin number, and GPIO flags as accepted by the "qe_pio_e" gpio-controller.
68 1.1) GPIO specifier best practices
71 A gpio-specifier should contain a flag indicating the GPIO polarity; active-
76 GPIO controller that achieves (or represents, for inputs) a logically asserted
79 the GPIO controller and the device, then the gpio-specifier will represent the
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| H A D | nvidia,tegra186-gpio.txt | 1 NVIDIA Tegra186 GPIO controllers
3 Tegra186 contains two GPIO controllers; a main controller and an "AON"
9 The Tegra186 GPIO controller allows software to set the IO direction of, and
10 read/write the value of, numerous GPIO signals. Routing of GPIO signals to
14 a) Security registers, which allow configuration of allowed access to the GPIO
17 varies between the different GPIO controllers.
20 that wishes to configure access to the GPIO registers needs access to these
21 registers to do so. Code which simply wishes to read or write GPIO data does not
24 b) GPIO registers, which allow manipulation of the GPIO signals. In some GPIO
27 documentation for rationale. Any particular GPIO client is expected to access
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| H A D | mscc_sgpio.txt | 1 Microsemi Corporation (MSCC) Serial GPIO driver
3 The MSCC serial GPIO extends the number or GPIO's on the system by
6 effective GPIO count can be extended by up to 128 GPIO's per
17 - gpio-controller : Marks the device node as a GPIO controller.
31 regular GPIO pins.
|
| H A D | snps,creg-gpio.txt | 1 GPIO via CREG (control registers) driver
15 - gpio-controller : Marks the device node as a GPIO controller.
16 - gpio-count: Number of GPIO pins.
18 - gpio-first-shift: Shift (in bits) of the first GPIO field in register
21 output to "1" (see picture). Applied to all GPIO ports.
23 output to "0" (see picture). Applied to all GPIO ports.
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| /openbmc/u-boot/arch/arm/dts/ |
| H A D | hi3798cv200-poplar.dts | 116 gpio-line-names = "GPIO-E", "",
118 "", "GPIO-F",
119 "", "GPIO-J";
124 gpio-line-names = "GPIO-H", "GPIO-I",
125 "GPIO-L", "GPIO-G",
126 "GPIO-K", "",
134 "GPIO-C", "",
135 "", "GPIO-B";
142 "", "GPIO-D",
150 "", "GPIO-A",
|
| /openbmc/u-boot/arch/x86/include/asm/arch-tangier/acpi/ |
| H A D | southcluster.asl | 33 /* GPIO Low Memory Region */
88 GPIO
105 If (^^GPIO.AVBL == One)
107 ^^GPIO.WFD3 = One
119 GPIO
134 If (^^^GPIO.AVBL == One)
136 ^^^GPIO.WFD3 = Zero
145 If (^^^GPIO.AVBL == One)
147 ^^^GPIO.WFD3 = One
175 "\\_SB.PCI0.GPIO", 0, ResourceConsumer, , ) { 110 }
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| /openbmc/phosphor-power/phosphor-power-sequencer/docs/config_file/ |
| H A D | gpio.md | 5 A General Purpose Input/Output (GPIO) that can be read to obtain the pgood
8 GPIO values are read using the libgpiod interface.
14 | line | yes | number | The libgpiod line offset of the GPIO. …
15 … | boolean (true or false) | If true, the GPIO value 0 indicates a true pgood status. If false,…
|
| /openbmc/u-boot/doc/device-tree-bindings/pinctrl/ |
| H A D | marvell,armada-37xx-pinctrl.txt | 1 * Marvell Armada 37xx SoC pin and GPIO controller
3 Each Armada 37xx SoC comes with two pin and GPIO controllers, one for the
6 GPIO and pin controller:
21 - reg: The first set of registers is for pinctrl/GPIO and the second
23 - interrupts: list of interrupts used by the GPIO
141 GPIO subnode:
144 and the common GPIO bindings used by client devices.
146 Required properties for the GPIO driver under the gpio subnode:
148 - gpio-controller: Marks the device node as a GPIO controller.
149 - #gpio-cells: Should be 2. The first cell is the GPIO number and the
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| /openbmc/openbmc/meta-yadro/meta-nicole/recipes-kernel/linux/linux-aspeed/ |
| H A D | 0001-Add-NCSI-channel-selector.patch | 6 NCSI channel number is selected depending on GPIO state of a pin
12 * GPIO pin value is 0: channel 0;
13 * GPIO pin value is 1: channel 1;
56 + * NCSI channel number is selected depending on GPIO state of a pin
79 + /* Read GPIO pin configuration */
82 + netdev_err(dev, "NCSI: GPIO configuration not found\n");
86 + /* Find GPIO chip */
89 + netdev_err(dev, "NCSI: GPIO chip not found\n");
93 + /* Read GPIO state */
96 + netdev_err(dev, "NCSI: Cannot get GPIO descriptor\n");
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| /openbmc/u-boot/doc/device-tree-bindings/spi/ |
| H A D | soft-spi.txt | 3 The soft SPI bus implementation allows the use of GPIO pins to simulate a
12 gpio-sck: GPIO to use for SPI clock (output)
14 gpio-mosi: GPIO to use for SPI MOSI line (output)
15 gpio-miso: GPIO to use for SPI MISO line (input)
20 The GPIOs should be specified as required by the GPIO controller referenced.
22 typically holds the GPIO number.
|
| /openbmc/u-boot/board/intel/cherryhill/ |
| H A D | cherryhill.c | 29 GPIO_PAD_CONF("N48: GP_CAMERASB00", GPIO, M1, GPO, LOW,
32 GPIO_PAD_CONF("N53: GP_CAMERASB01", GPIO, M1, GPO, LOW,
35 GPIO_PAD_CONF("N46: GP_CAMERASB02", GPIO, M1, GPO, LOW,
38 GPIO_PAD_CONF("N51: GP_CAMERASB03", GPIO, M1, GPO, LOW,
41 GPIO_PAD_CONF("N56: GP_CAMERASB04", GPIO, M1, GPO, LOW,
44 GPIO_PAD_CONF("N45: GP_CAMERASB05", GPIO, M1, GPO, LOW,
47 GPIO_PAD_CONF("N49: GP_CAMERASB06", GPIO, M1, GPO, LOW,
50 GPIO_PAD_CONF("N54: GP_CAMERASB07", GPIO, M1, GPO, LOW,
53 GPIO_PAD_CONF("N47: GP_CAMERASB08", GPIO, M1, GPO, LOW,
56 GPIO_PAD_CONF("N52: GP_CAMERASB09", GPIO, M1, GPO, LOW,
[all …]
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| /openbmc/u-boot/drivers/pinctrl/renesas/ |
| H A D | Kconfig | 16 the GPIO definitions and pin control functions for each available
26 the GPIO definitions and pin control functions for each available
36 the GPIO definitions and pin control functions for each available
46 the GPIO definitions and pin control functions for each available
56 the GPIO definitions and pin control functions for each available
66 the GPIO definitions and pin control functions for each available
76 the GPIO definitions and pin control functions for each available
86 the GPIO definitions and pin control functions for each available
96 the GPIO definitions and pin control functions for each available
106 the GPIO definitions and pin control functions for each available
|
| /openbmc/x86-power-control/ |
| H A D | README.md | 18 x86-power-control uses default json file (power-config-host0.json) for GPIO
24 Definitions can be configured by two type: GPIO and DBUS
26 ### GPIO subsection
28 For the platform having direct GPIO access can use the type GPIO and define like
35 "Type": "GPIO"
41 For the platform not having direct GPIO access can use dbus based event monitor
70 The POST Complete GPIO is usually held asserted by BIOS after POST complete and
|
| /openbmc/docs/designs/ |
| H A D | device-tree-gpio-naming.md | 1 # Device Tree GPIO Naming in OpenBMC
11 The Linux kernel has deprecated the use of sysfs to interact with the GPIO
19 for these GPIO names and if you want userspace code to be able to be consistent
24 The kernel [documentation][2] has a good summary of the GPIO subsystem. The
42 naming convention and then the sub bullets list the common GPIO names to be used
63 Below are input GPIO names specific to Host ready. The name of Host ready GPIO
113 Output GPIO set by the power managing application that indicates to the hardware
119 GPIO, the hardware can then take actions such as reducing the system's
124 Output GPIO set by the power managing applications. The IBM Common Form Factor
132 This GPIO value represents the status of standby power regulator fault detection
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|
| /openbmc/phosphor-gpio-monitor/ |
| H A D | README.md | 1 # GPIO Monitoring
8 take action if requested. This implementation uses GPIO keys and only supports
9 monitoring single GPIO line, for multiple lines, user has to run this daemon
14 This daemon accepts command line parameter as a well-defined GPIO configuration
22 easy to add list of gpios into JSON config file and it also supports of GPIO
35 3. GpioNum: GPIO offset, this field is optional if LineName is defined.
46 depending on the current GPIO value, the systemd services for INIT_HIGH and
81 This daemon accepts command line parameter as a well-defined GPIO configuration
91 GPIO line by name defined in kernel.
103 3. GpioNum: GPIO offset, this field is optional if LineName is defined.
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|