Searched refs:GMAC0_DMA_TX_CTRL_ADDR (Results 1 – 2 of 2) sorted by relevance
28 #define GMAC0_DMA_TX_CTRL_ADDR (GMAC0_REG_BASE + 0x200) macro30 (GMAC0_DMA_TX_CTRL_ADDR + GMAC_DMA_PTR_OFFSET)32 (GMAC0_DMA_TX_CTRL_ADDR + GMAC_DMA_ADDR_LOW_OFFSET)34 (GMAC0_DMA_TX_CTRL_ADDR + GMAC_DMA_ADDR_HIGH_OFFSET)36 (GMAC0_DMA_TX_CTRL_ADDR + GMAC_DMA_STATUS0_OFFSET)38 (GMAC0_DMA_TX_CTRL_ADDR + GMAC_DMA_STATUS1_OFFSET)
62 control = readl(GMAC0_DMA_TX_CTRL_ADDR); in dma_ctrlflags()63 writel(control | D64_XC_PD, GMAC0_DMA_TX_CTRL_ADDR); in dma_ctrlflags()64 if (readl(GMAC0_DMA_TX_CTRL_ADDR) & D64_XC_PD) { in dma_ctrlflags()69 writel(control, GMAC0_DMA_TX_CTRL_ADDR); in dma_ctrlflags()102 readl(GMAC0_DMA_TX_CTRL_ADDR), in dma_tx_dump()277 (readl(GMAC0_DMA_TX_CTRL_ADDR) & D64_XC_BL_MASK) in dma_init()488 writel(D64_XC_SE, GMAC0_DMA_TX_CTRL_ADDR); in gmac_disable_dma()499 writel(0, GMAC0_DMA_TX_CTRL_ADDR); in gmac_disable_dma()539 control = readl(GMAC0_DMA_TX_CTRL_ADDR); in gmac_enable_dma()545 writel(control, GMAC0_DMA_TX_CTRL_ADDR); in gmac_enable_dma()