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Searched refs:GIC_VP_MASK_CMP_MSK (Results 1 – 2 of 2) sorted by relevance

/openbmc/qemu/hw/intc/
H A Dmips_gic.c43 (gic->vps[vp].mask & GIC_VP_MASK_CMP_MSK)) { in mips_gic_set_vp_irq()
45 ored_level |= (gic->vps[vp].pend & GIC_VP_MASK_CMP_MSK) >> in mips_gic_set_vp_irq()
202 (gic->vps[vp_index].mask & GIC_VP_MASK_CMP_MSK)) { in gic_timer_expire_cb()
/openbmc/qemu/include/hw/intc/
H A Dmips_gic.h155 #define GIC_VP_MASK_CMP_MSK (MSK(1) << GIC_VP_MASK_CMP_SHF) macro