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Searched refs:GIC_NR_APRS (Results 1 – 3 of 3) sorted by relevance

/openbmc/qemu/include/hw/intc/
H A Darm_gic_common.h38 #define GIC_NR_APRS (MAX_NR_GROUP_PRIO / 32) macro
117 uint32_t apr[GIC_NR_APRS][GIC_NCPU];
118 uint32_t nsapr[GIC_NR_APRS][GIC_NCPU];
/openbmc/qemu/hw/intc/
H A Darm_gic_common.c121 VMSTATE_UINT32_2DARRAY(apr, GICState, GIC_NR_APRS, GIC_NCPU),
122 VMSTATE_UINT32_2DARRAY(nsapr, GICState, GIC_NR_APRS, GIC_NCPU),
H A Darm_gic.c519 for (i = 0; i < GIC_NR_APRS; i++) { in gic_get_prio_from_apr_bits()
557 for (i = 0; i < GIC_NR_APRS; i++) { in gic_drop_prio()
1653 int nr_aprs = gic_is_vcpu(cpu) ? GIC_VIRT_NR_APRS : GIC_NR_APRS; in gic_cpu_read()
1671 if (regno >= GIC_NR_APRS || s->revision != 2 || !gic_has_groups(s) || in gic_cpu_read()
1740 int nr_aprs = gic_is_vcpu(cpu) ? GIC_VIRT_NR_APRS : GIC_NR_APRS; in gic_cpu_write()
1760 if (regno >= GIC_NR_APRS || s->revision != 2) { in gic_cpu_write()