Searched refs:GIC_CPU_CTRL (Results 1 – 6 of 6) sorted by relevance
| /openbmc/linux/arch/arm/mach-tegra/ |
| H A D | irq.c | 51 writel_relaxed(0x1E0, tegra_gic_cpu_base + GIC_CPU_CTRL); in tegra_gic_notifier()
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| /openbmc/linux/tools/testing/selftests/kvm/aarch64/ |
| H A D | vgic_init.c | 377 #define GIC_CPU_CTRL 0x00 macro
389 KVM_VGIC_V2_ATTR(GIC_CPU_CTRL, 0)); in test_v2_uaccess_cpuif_no_vcpus()
394 KVM_VGIC_V2_ATTR(GIC_CPU_CTRL, 0), &val); in test_v2_uaccess_cpuif_no_vcpus()
399 KVM_VGIC_V2_ATTR(GIC_CPU_CTRL, 0), &val); in test_v2_uaccess_cpuif_no_vcpus()
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| /openbmc/linux/include/linux/irqchip/ |
| H A D | arm-gic.h | 10 #define GIC_CPU_CTRL 0x00 macro
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| /openbmc/linux/arch/arm64/kvm/vgic/ |
| H A D | vgic-mmio-v2.c | 284 case GIC_CPU_CTRL: in vgic_mmio_read_vcpuif()
331 case GIC_CPU_CTRL: in vgic_mmio_write_vcpuif()
467 REGISTER_DESC_WITH_LENGTH(GIC_CPU_CTRL,
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| /openbmc/linux/drivers/irqchip/ |
| H A D | irq-gic.c | 460 bypass = readl(cpu_base + GIC_CPU_CTRL); in gic_cpu_if_up()
463 writel_relaxed(bypass | mode | GICC_ENABLE, cpu_base + GIC_CPU_CTRL); in gic_cpu_if_up()
539 val = readl(cpu_base + GIC_CPU_CTRL); in gic_cpu_if_down()
541 writel_relaxed(val, cpu_base + GIC_CPU_CTRL); in gic_cpu_if_down()
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| H A D | irq-hip04.c | 293 writel_relaxed(1, base + GIC_CPU_CTRL); in hip04_irq_cpu_init()
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