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Searched refs:GICR_ISPENDR0 (Results 1 – 7 of 7) sorted by relevance

/openbmc/linux/tools/testing/selftests/kvm/include/aarch64/
H A Dgic_v3.h56 #define GICR_ISPENDR0 GICD_ISPENDR macro
/openbmc/linux/Documentation/virt/kvm/devices/
H A Darm-vgic-v3.rst99 GICR_ISPENDR0, GICD_ICPENDR, and GICR_ICPENDR0. These registers behave
132 GICR_ISPENDR0 registers get/set the value of the latched pending state for
/openbmc/qemu/hw/intc/
H A Darm_gicv3_kvm.c392 kvm_gicr_access(s, GICR_ISPENDR0, ncpu, &reg, true); in kvm_arm_gicv3_put()
547 kvm_gicr_access(s, GICR_ISPENDR0, ncpu, &reg, false); in kvm_arm_gicv3_get()
H A Darm_gicv3_redist.c395 case GICR_ISPENDR0: in gicr_readl()
552 case GICR_ISPENDR0: in gicr_writel()
H A Dgicv3_internal.h106 #define GICR_ISPENDR0 (GICR_SGI_OFFSET + 0x0200) macro
/openbmc/linux/include/linux/irqchip/
H A Darm-gic-v3.h233 #define GICR_ISPENDR0 GICD_ISPENDR macro
/openbmc/linux/arch/arm64/kvm/vgic/
H A Dvgic-mmio-v3.c727 REGISTER_DESC_WITH_LENGTH_UACCESS(SZ_64K + GICR_ISPENDR0,