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Searched refs:GICR_ISENABLER0 (Results 1 – 6 of 6) sorted by relevance

/openbmc/linux/tools/testing/selftests/kvm/include/aarch64/
H A Dgic_v3.h54 #define GICR_ISENABLER0 GICD_ISENABLER macro
/openbmc/qemu/hw/intc/
H A Darm_gicv3_redist.c379 case GICR_ISENABLER0: in gicr_readl()
530 case GICR_ISENABLER0: in gicr_writel()
H A Darm_gicv3_kvm.c380 kvm_gicr_access(s, GICR_ISENABLER0, ncpu, &reg, true); in kvm_arm_gicv3_put()
541 kvm_gicr_access(s, GICR_ISENABLER0, ncpu, &reg, false); in kvm_arm_gicv3_get()
H A Dgicv3_internal.h101 #define GICR_ISENABLER0 (GICR_SGI_OFFSET + 0x0100) macro
/openbmc/linux/include/linux/irqchip/
H A Darm-gic-v3.h231 #define GICR_ISENABLER0 GICD_ISENABLER macro
/openbmc/linux/arch/arm64/kvm/vgic/
H A Dvgic-mmio-v3.c714 REGISTER_DESC_WITH_LENGTH_UACCESS(SZ_64K + GICR_ISENABLER0,