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Searched refs:GICH_LR0 (Results 1 – 3 of 3) sorted by relevance

/openbmc/qemu/hw/intc/
H A Dgic_internal.h111 REG32(GICH_LR0, 0x100)
112 FIELD(GICH_LR0, VirtualID, 0, 10)
113 FIELD(GICH_LR0, PhysicalID, 10, 10)
114 FIELD(GICH_LR0, CPUID, 10, 3)
115 FIELD(GICH_LR0, EOI, 19, 1)
116 FIELD(GICH_LR0, Priority, 23, 5)
117 FIELD(GICH_LR0, State, 28, 2)
118 FIELD(GICH_LR0, Grp1, 30, 1)
119 FIELD(GICH_LR0, HW, 31, 1)
138 #define GICH_LR_EOI(entry) (FIELD_EX32(entry, GICH_LR0, EOI))
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/openbmc/linux/arch/arm64/kvm/vgic/
H A Dvgic-v2.c18 writel_relaxed(val, base + GICH_LR0 + (lr * 4)); in vgic_v2_write_lr()
418 cpu_if->vgic_lr[i] = readl_relaxed(base + GICH_LR0 + (i * 4)); in save_lrs()
420 writel_relaxed(0, base + GICH_LR0 + (i * 4)); in save_lrs()
452 base + GICH_LR0 + (i * 4)); in vgic_v2_restore_state()
/openbmc/linux/include/linux/irqchip/
H A Darm-gic.h85 #define GICH_LR0 0x100 macro