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Searched refs:GICD_ICPENDR (Results 1 – 9 of 9) sorted by relevance

/openbmc/qemu/hw/intc/
H A Darm_gicv3_dist.c450 case GICD_ICPENDR ... GICD_ICPENDR + 0x7f: in gicd_readl()
452 offset - GICD_ICPENDR); in gicd_readl()
653 case GICD_ICPENDR ... GICD_ICPENDR + 0x7f: in gicd_writel()
655 offset - GICD_ICPENDR, value); in gicd_writel()
H A Dgicv3_internal.h44 #define GICD_ICPENDR 0x0280 macro
H A Darm_gicv3_kvm.c447 kvm_dist_putbmp(s, GICD_ISPENDR, GICD_ICPENDR, s->pending); in kvm_arm_gicv3_put()
/openbmc/linux/tools/testing/selftests/kvm/include/aarch64/
H A Dgic_v3.h20 #define GICD_ICPENDR 0x0280 macro
/openbmc/linux/include/linux/irqchip/
H A Darm-gic-v3.h26 #define GICD_ICPENDR 0x0280 macro
234 #define GICR_ICPENDR0 GICD_ICPENDR
/openbmc/linux/tools/testing/selftests/kvm/lib/aarch64/
H A Dgic_v3.c258 gicv3_write_reg(intid, GICD_ICPENDR, 32, 1, 1); in gicv3_irq_clear_pending()
/openbmc/linux/Documentation/virt/kvm/devices/
H A Darm-vgic-v3.rst99 GICR_ISPENDR0, GICD_ICPENDR, and GICR_ICPENDR0. These registers behave
159 Accesses to GICD_ICPENDR register region and GICR_ICPENDR0 registers have
/openbmc/linux/drivers/irqchip/
H A Dirq-gic-v3.c349 case GICD_ICPENDR: in convert_offset_index()
451 reg = val ? GICD_ISPENDR : GICD_ICPENDR; in gic_irq_set_irqchip_state()
/openbmc/linux/arch/arm64/kvm/vgic/
H A Dvgic-mmio-v3.c642 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICPENDR,