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Searched refs:GET_IDREG (Results 1 – 8 of 8) sorted by relevance

/openbmc/qemu/hw/intc/
H A Darmv7m_nvic.c1267 return GET_IDREG(isar, ID_PFR0); in nvic_readl()
1272 return GET_IDREG(isar, ID_PFR1); in nvic_readl()
1277 return GET_IDREG(isar, ID_DFR0); in nvic_readl()
1282 return GET_IDREG(isar, ID_AFR0); in nvic_readl()
1287 return GET_IDREG(isar, ID_MMFR0); in nvic_readl()
1292 return GET_IDREG(isar, ID_MMFR1); in nvic_readl()
1297 return GET_IDREG(isar, ID_MMFR2); in nvic_readl()
1302 return GET_IDREG(isar, ID_MMFR3); in nvic_readl()
1307 return GET_IDREG(&cpu->isar, ID_ISAR0); in nvic_readl()
1312 return GET_IDREG(&cpu->isar, ID_ISAR1); in nvic_readl()
[all …]
/openbmc/qemu/target/arm/tcg/
H A Dcpu64.c1202 u = GET_IDREG(isar, CLIDR); in aarch64_max_tcg_initfn()
1217 t = GET_IDREG(isar, ID_AA64ISAR0); in aarch64_max_tcg_initfn()
1234 t = GET_IDREG(isar, ID_AA64ISAR1); in aarch64_max_tcg_initfn()
1250 t = GET_IDREG(isar, ID_AA64ISAR2); in aarch64_max_tcg_initfn()
1259 t = GET_IDREG(isar, ID_AA64PFR0); in aarch64_max_tcg_initfn()
1270 t = GET_IDREG(isar, ID_AA64PFR1); in aarch64_max_tcg_initfn()
1286 t = GET_IDREG(isar, ID_AA64MMFR0); in aarch64_max_tcg_initfn()
1296 t = GET_IDREG(isar, ID_AA64MMFR1); in aarch64_max_tcg_initfn()
1311 t = GET_IDREG(isar, ID_AA64MMFR2); in aarch64_max_tcg_initfn()
1327 t = GET_IDREG(isa in aarch64_cpu_register_types()
[all...]
H A Dcpu32.c29 t = GET_IDREG(isar, ID_ISAR5); in aa32_max_features()
38 t = GET_IDREG(isar, ID_ISAR6); in aa32_max_features()
60 t = GET_IDREG(isar, ID_MMFR4); in aa32_max_features()
70 t = GET_IDREG(isar, ID_PFR0); in aa32_max_features()
76 t = GET_IDREG(isar, ID_PFR2); in aa32_max_features()
81 t = GET_IDREG(isar, ID_DFR0); in aa32_max_features()
/openbmc/qemu/target/arm/
H A Dcpu64.c264 uint64_t t = GET_IDREG(&cpu->isar, ID_AA64ZFR0); in arm_cpu_sve_finalize()
514 isar1 = GET_IDREG(isar, ID_AA64ISAR1); in arm_cpu_pauth_finalize()
520 isar2 = GET_IDREG(isar, ID_AA64ISAR2); in arm_cpu_pauth_finalize()
630 t = GET_IDREG(&cpu->isar, ID_AA64MMFR0); in arm_cpu_lpa2_finalize()
H A Dhelper.c5198 uint64_t pfr1 = GET_IDREG(&cpu->isar, ID_PFR1);
5209 uint64_t pfr0 = GET_IDREG(&cpu->isar, ID_AA64PFR0); in id_pfr1_read()
6291 .resetvalue = GET_IDREG(isar, ID_PFR0)}, in register_cp_regs_for_features()
6302 .resetvalue = GET_IDREG(isar, ID_PFR1), in register_cp_regs_for_features()
6314 .resetvalue = GET_IDREG(isar, ID_DFR0)}, in register_cp_regs_for_features()
6319 .resetvalue = GET_IDREG(isar, ID_AFR0)}, in register_cp_regs_for_features()
6324 .resetvalue = GET_IDREG(isar, ID_MMFR0)}, in register_cp_regs_for_features()
6329 .resetvalue = GET_IDREG(isar, ID_MMFR1)}, in register_cp_regs_for_features()
6334 .resetvalue = GET_IDREG(isar, ID_MMFR2)}, in register_cp_regs_for_features()
6339 .resetvalue = GET_IDREG(isa in register_cp_regs_for_features()
[all...]
H A Dcpu.c1780 u = GET_IDREG(isar, ID_ISAR6); in arm_cpu_post_init()
1817 t = GET_IDREG(isar, ID_AA64ISAR0); in arm_cpu_post_init()
1827 t = GET_IDREG(isar, ID_AA64ISAR1); in arm_cpu_post_init()
1835 u = GET_IDREG(isar, ID_ISAR5); in arm_cpu_post_init()
1843 u = GET_IDREG(isar, ID_ISAR6); in arm_cpu_post_init()
1888 u = GET_IDREG(isar, ID_ISAR2); in arm_cpu_post_init()
1893 u = GET_IDREG(isar, ID_ISAR3);
H A Dcpu.h902 #define GET_IDREG(ISAR, REG) \
2363 return (GET_IDREG(&cpu->isar, CLIDR) & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0;
895 #define GET_IDREG( global() macro
/openbmc/qemu/target/arm/hvf/
H A Dhvf.c739 id_aa64mmfr0 = GET_IDREG(isar, ID_AA64MMFR0); in hvf_put_registers()
806 GET_IDREG(&host_isar, ID_AA64PFR1) & ~R_ID_AA64PFR1_SME_MASK); in hvf_put_registers()
823 if ((GET_IDREG(&host_isar, ID_AA64PFR0) & 0xff) != 0x11) { in hvf_set_reg()