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Searched refs:GENS0__CRT_INTR_MASK (Results 1 – 18 of 18) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_sh_mask.h7181 #define GENS0__CRT_INTR_MASK 0x00000080L macro
H A Ddce_8_0_sh_mask.h10639 #define GENS0__CRT_INTR_MASK 0x80 macro
H A Ddce_10_0_sh_mask.h11023 #define GENS0__CRT_INTR_MASK 0x80 macro
H A Ddce_11_0_sh_mask.h10835 #define GENS0__CRT_INTR_MASK 0x80 macro
H A Ddce_11_2_sh_mask.h12089 #define GENS0__CRT_INTR_MASK 0x80 macro
H A Ddce_12_0_sh_mask.h2219 #define GENS0__CRT_INTR_MASK … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_sh_mask.h256 #define GENS0__CRT_INTR_MASK … macro
H A Ddcn_1_0_sh_mask.h858 #define GENS0__CRT_INTR_MASK … macro
H A Ddcn_3_0_1_sh_mask.h351 #define GENS0__CRT_INTR_MASK … macro
H A Ddcn_3_2_1_sh_mask.h4454 #define GENS0__CRT_INTR_MASK … macro
H A Ddcn_3_1_2_sh_mask.h351 #define GENS0__CRT_INTR_MASK … macro
H A Ddcn_3_1_5_sh_mask.h5159 #define GENS0__CRT_INTR_MASK … macro
H A Ddcn_3_1_6_sh_mask.h366 #define GENS0__CRT_INTR_MASK … macro
H A Ddcn_3_1_4_sh_mask.h7806 #define GENS0__CRT_INTR_MASK … macro
H A Ddcn_3_0_2_sh_mask.h269 #define GENS0__CRT_INTR_MASK … macro
H A Ddcn_2_0_0_sh_mask.h269 #define GENS0__CRT_INTR_MASK … macro
H A Ddcn_3_0_0_sh_mask.h250 #define GENS0__CRT_INTR_MASK … macro
H A Ddcn_3_2_0_sh_mask.h4453 #define GENS0__CRT_INTR_MASK … macro