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Searched refs:GENMO_WT__VGA_HSYNC_POL_MASK (Results 1 – 18 of 18) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_sh_mask.h7175 #define GENMO_WT__VGA_HSYNC_POL_MASK 0x00000040L macro
H A Ddce_8_0_sh_mask.h10615 #define GENMO_WT__VGA_HSYNC_POL_MASK 0x40 macro
H A Ddce_10_0_sh_mask.h10999 #define GENMO_WT__VGA_HSYNC_POL_MASK 0x40 macro
H A Ddce_11_0_sh_mask.h10811 #define GENMO_WT__VGA_HSYNC_POL_MASK 0x40 macro
H A Ddce_11_2_sh_mask.h12065 #define GENMO_WT__VGA_HSYNC_POL_MASK 0x40 macro
H A Ddce_12_0_sh_mask.h2213 #define GENMO_WT__VGA_HSYNC_POL_MASK … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_sh_mask.h250 #define GENMO_WT__VGA_HSYNC_POL_MASK … macro
H A Ddcn_3_0_1_sh_mask.h345 #define GENMO_WT__VGA_HSYNC_POL_MASK … macro
H A Ddcn_3_2_1_sh_mask.h4448 #define GENMO_WT__VGA_HSYNC_POL_MASK … macro
H A Ddcn_1_0_sh_mask.h852 #define GENMO_WT__VGA_HSYNC_POL_MASK … macro
H A Ddcn_3_1_2_sh_mask.h345 #define GENMO_WT__VGA_HSYNC_POL_MASK … macro
H A Ddcn_3_1_5_sh_mask.h5153 #define GENMO_WT__VGA_HSYNC_POL_MASK … macro
H A Ddcn_3_1_6_sh_mask.h360 #define GENMO_WT__VGA_HSYNC_POL_MASK … macro
H A Ddcn_3_0_2_sh_mask.h263 #define GENMO_WT__VGA_HSYNC_POL_MASK … macro
H A Ddcn_3_1_4_sh_mask.h7800 #define GENMO_WT__VGA_HSYNC_POL_MASK … macro
H A Ddcn_3_0_0_sh_mask.h244 #define GENMO_WT__VGA_HSYNC_POL_MASK … macro
H A Ddcn_2_0_0_sh_mask.h263 #define GENMO_WT__VGA_HSYNC_POL_MASK … macro
H A Ddcn_3_2_0_sh_mask.h4447 #define GENMO_WT__VGA_HSYNC_POL_MASK … macro