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Searched refs:GENMO_RD__VGA_RAM_EN_MASK (Results 1 – 18 of 18) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_sh_mask.h7165 #define GENMO_RD__VGA_RAM_EN_MASK 0x00000002L macro
H A Ddce_8_0_sh_mask.h10621 #define GENMO_RD__VGA_RAM_EN_MASK 0x2 macro
H A Ddce_10_0_sh_mask.h11005 #define GENMO_RD__VGA_RAM_EN_MASK 0x2 macro
H A Ddce_11_0_sh_mask.h10817 #define GENMO_RD__VGA_RAM_EN_MASK 0x2 macro
H A Ddce_11_2_sh_mask.h12071 #define GENMO_RD__VGA_RAM_EN_MASK 0x2 macro
H A Ddce_12_0_sh_mask.h2252 #define GENMO_RD__VGA_RAM_EN_MASK … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_sh_mask.h289 #define GENMO_RD__VGA_RAM_EN_MASK … macro
H A Ddcn_1_0_sh_mask.h891 #define GENMO_RD__VGA_RAM_EN_MASK … macro
H A Ddcn_3_0_1_sh_mask.h382 #define GENMO_RD__VGA_RAM_EN_MASK … macro
H A Ddcn_3_2_1_sh_mask.h4487 #define GENMO_RD__VGA_RAM_EN_MASK … macro
H A Ddcn_3_1_2_sh_mask.h382 #define GENMO_RD__VGA_RAM_EN_MASK … macro
H A Ddcn_3_1_5_sh_mask.h5192 #define GENMO_RD__VGA_RAM_EN_MASK … macro
H A Ddcn_3_1_6_sh_mask.h399 #define GENMO_RD__VGA_RAM_EN_MASK … macro
H A Ddcn_3_1_4_sh_mask.h7837 #define GENMO_RD__VGA_RAM_EN_MASK … macro
H A Ddcn_3_0_2_sh_mask.h302 #define GENMO_RD__VGA_RAM_EN_MASK … macro
H A Ddcn_2_0_0_sh_mask.h302 #define GENMO_RD__VGA_RAM_EN_MASK … macro
H A Ddcn_3_0_0_sh_mask.h283 #define GENMO_RD__VGA_RAM_EN_MASK … macro
H A Ddcn_3_2_0_sh_mask.h4486 #define GENMO_RD__VGA_RAM_EN_MASK … macro