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Searched refs:GENMASK_ULL (Results 1 – 6 of 6) sorted by relevance

/openbmc/qemu/hw/riscv/
H A Driscv-iommu-bits.h18 #ifndef GENMASK_ULL
19 #define GENMASK_ULL(h, l) (((~0ULL) >> (63 - (h) + (l))) << (l)) macro
33 #define RISCV_IOMMU_FQ_HDR_CAUSE GENMASK_ULL(11, 0)
34 #define RISCV_IOMMU_FQ_HDR_PID GENMASK_ULL(31, 12)
36 #define RISCV_IOMMU_FQ_HDR_TTYPE GENMASK_ULL(39, 34)
37 #define RISCV_IOMMU_FQ_HDR_DID GENMASK_ULL(63, 40)
48 #define RISCV_IOMMU_PREQ_HDR_PID GENMASK_ULL(31, 12)
52 #define RISCV_IOMMU_PREQ_HDR_DID GENMASK_ULL(63, 40)
58 #define RISCV_IOMMU_PREQ_PAYLOAD_M GENMASK_ULL(2, 0)
59 #define RISCV_IOMMU_PREQ_PRG_INDEX GENMASK_ULL(11, 3)
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/openbmc/qemu/tests/qtest/libqos/
H A Driscv-iommu.h18 #ifndef GENMASK_ULL
19 #define GENMASK_ULL(h, l) (((~0ULL) >> (63 - (h) + (l))) << (l)) macro
38 #define RISCV_IOMMU_CAP_VERSION GENMASK_ULL(7, 0)
42 #define RISCV_IOMMU_DDTP_MODE GENMASK_ULL(3, 0)
66 #define RISCV_IOMMU_REG_IVEC_CIV GENMASK_ULL(3, 0)
67 #define RISCV_IOMMU_REG_IVEC_FIV GENMASK_ULL(7, 4)
68 #define RISCV_IOMMU_REG_IVEC_PMIV GENMASK_ULL(11, 8)
69 #define RISCV_IOMMU_REG_IVEC_PIV GENMASK_ULL(15, 12)
/openbmc/u-boot/drivers/firmware/
H A Dti_sci.h508 #define TISCI_ADDR_LOW_MASK GENMASK_ULL(31, 0)
509 #define TISCI_ADDR_HIGH_MASK GENMASK_ULL(63, 32)
/openbmc/u-boot/include/linux/
H A Dbitops.h32 #define GENMASK_ULL(h, l) \ macro
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-kernel/turbostat/
H A Dturbostat.bb85 …echo "#define GENMASK_ULL(h, l) (((~0ULL) << (l)) & (~0ULL >> (sizeof(long long) * 8 - 1 - (h))))"…
/openbmc/u-boot/drivers/net/
H A Dmvpp2.c1302 tx_desc->pp22.buf_dma_addr_ptp &= ~GENMASK_ULL(40, 0); in mvpp2_txdesc_dma_addr_set()
1353 return rx_desc->pp22.buf_dma_addr_key_hash & GENMASK_ULL(40, 0); in mvpp2_rxdesc_dma_addr_get()
1362 return rx_desc->pp22.buf_cookie_misc & GENMASK_ULL(40, 0); in mvpp2_rxdesc_cookie_get()