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Searched refs:GENFC_RD__VSYNC_SEL_R_MASK (Results 1 – 18 of 18) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_sh_mask.h7153 #define GENFC_RD__VSYNC_SEL_R_MASK 0x00000008L macro
H A Ddce_8_0_sh_mask.h10635 #define GENFC_RD__VSYNC_SEL_R_MASK 0x8 macro
H A Ddce_10_0_sh_mask.h11019 #define GENFC_RD__VSYNC_SEL_R_MASK 0x8 macro
H A Ddce_11_0_sh_mask.h10831 #define GENFC_RD__VSYNC_SEL_R_MASK 0x8 macro
H A Ddce_11_2_sh_mask.h12085 #define GENFC_RD__VSYNC_SEL_R_MASK 0x8 macro
H A Ddce_12_0_sh_mask.h2243 #define GENFC_RD__VSYNC_SEL_R_MASK … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_sh_mask.h280 #define GENFC_RD__VSYNC_SEL_R_MASK … macro
H A Ddcn_1_0_sh_mask.h882 #define GENFC_RD__VSYNC_SEL_R_MASK … macro
H A Ddcn_3_0_1_sh_mask.h373 #define GENFC_RD__VSYNC_SEL_R_MASK … macro
H A Ddcn_3_2_1_sh_mask.h4478 #define GENFC_RD__VSYNC_SEL_R_MASK … macro
H A Ddcn_3_1_2_sh_mask.h373 #define GENFC_RD__VSYNC_SEL_R_MASK … macro
H A Ddcn_3_1_5_sh_mask.h5183 #define GENFC_RD__VSYNC_SEL_R_MASK … macro
H A Ddcn_3_1_6_sh_mask.h390 #define GENFC_RD__VSYNC_SEL_R_MASK … macro
H A Ddcn_3_1_4_sh_mask.h7828 #define GENFC_RD__VSYNC_SEL_R_MASK … macro
H A Ddcn_3_0_2_sh_mask.h293 #define GENFC_RD__VSYNC_SEL_R_MASK … macro
H A Ddcn_2_0_0_sh_mask.h293 #define GENFC_RD__VSYNC_SEL_R_MASK … macro
H A Ddcn_3_0_0_sh_mask.h274 #define GENFC_RD__VSYNC_SEL_R_MASK … macro
H A Ddcn_3_2_0_sh_mask.h4477 #define GENFC_RD__VSYNC_SEL_R_MASK … macro