Searched refs:GENCONF_PORT_CTRL0_CLK_DIV_PHASE_CLR (Results 1 – 2 of 2) sorted by relevance
671 #define GENCONF_PORT_CTRL0_CLK_DIV_PHASE_CLR BIT(31) macro
1672 val |= GENCONF_PORT_CTRL0_CLK_DIV_PHASE_CLR; in mvpp22_gop_init()