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Searched refs:GDS_CONFIG__SH3_GPR_PHASE_SEL_MASK (Results 1 – 11 of 11) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h4316 #define GDS_CONFIG__SH3_GPR_PHASE_SEL_MASK 0x00000180L macro
H A Dgfx_7_2_sh_mask.h14619 #define GDS_CONFIG__SH3_GPR_PHASE_SEL_MASK 0x180 macro
H A Dgfx_8_1_sh_mask.h17135 #define GDS_CONFIG__SH3_GPR_PHASE_SEL_MASK 0x180 macro
H A Dgfx_8_0_sh_mask.h16547 #define GDS_CONFIG__SH3_GPR_PHASE_SEL_MASK 0x180 macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h4729 #define GDS_CONFIG__SH3_GPR_PHASE_SEL_MASK … macro
H A Dgc_9_1_sh_mask.h4201 #define GDS_CONFIG__SH3_GPR_PHASE_SEL_MASK … macro
H A Dgc_9_2_1_sh_mask.h4107 #define GDS_CONFIG__SH3_GPR_PHASE_SEL_MASK … macro
H A Dgc_9_4_3_sh_mask.h5157 #define GDS_CONFIG__SH3_GPR_PHASE_SEL_MASK … macro
H A Dgc_9_4_2_sh_mask.h6838 #define GDS_CONFIG__SH3_GPR_PHASE_SEL_MASK … macro
H A Dgc_10_1_0_sh_mask.h9000 #define GDS_CONFIG__SH3_GPR_PHASE_SEL_MASK … macro
H A Dgc_10_3_0_sh_mask.h9177 #define GDS_CONFIG__SH3_GPR_PHASE_SEL_MASK … macro