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Searched refs:GDS_CONFIG__SH1_GPR_PHASE_SEL__SHIFT (Results 1 – 11 of 11) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h4313 #define GDS_CONFIG__SH1_GPR_PHASE_SEL__SHIFT 0x00000003 macro
H A Dgfx_7_2_sh_mask.h14616 #define GDS_CONFIG__SH1_GPR_PHASE_SEL__SHIFT 0x3 macro
H A Dgfx_8_0_sh_mask.h16544 #define GDS_CONFIG__SH1_GPR_PHASE_SEL__SHIFT 0x3 macro
H A Dgfx_8_1_sh_mask.h17132 #define GDS_CONFIG__SH1_GPR_PHASE_SEL__SHIFT 0x3 macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h4723 #define GDS_CONFIG__SH1_GPR_PHASE_SEL__SHIFT … macro
H A Dgc_9_2_1_sh_mask.h4101 #define GDS_CONFIG__SH1_GPR_PHASE_SEL__SHIFT … macro
H A Dgc_9_1_sh_mask.h4195 #define GDS_CONFIG__SH1_GPR_PHASE_SEL__SHIFT … macro
H A Dgc_9_4_3_sh_mask.h5146 #define GDS_CONFIG__SH1_GPR_PHASE_SEL__SHIFT … macro
H A Dgc_9_4_2_sh_mask.h6828 #define GDS_CONFIG__SH1_GPR_PHASE_SEL__SHIFT … macro
H A Dgc_10_1_0_sh_mask.h8993 #define GDS_CONFIG__SH1_GPR_PHASE_SEL__SHIFT … macro
H A Dgc_10_3_0_sh_mask.h9170 #define GDS_CONFIG__SH1_GPR_PHASE_SEL__SHIFT … macro