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Searched refs:GC_BASE__INST1_SEG0 (Results 1 – 14 of 14) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/
H A Dcyan_skillfish_ip_offset.h323 #define GC_BASE__INST1_SEG0 0 macro
H A Dnavi10_ip_offset.h358 #define GC_BASE__INST1_SEG0 0 macro
H A Dnavi12_ip_offset.h495 #define GC_BASE__INST1_SEG0 0 macro
H A Ddimgrey_cavefish_ip_offset.h517 #define GC_BASE__INST1_SEG0 0 macro
H A Dvega20_ip_offset.h385 #define GC_BASE__INST1_SEG0 0 macro
H A Dnavi14_ip_offset.h495 #define GC_BASE__INST1_SEG0 0 macro
H A Dsienna_cichlid_ip_offset.h502 #define GC_BASE__INST1_SEG0 0 macro
H A Dbeige_goby_ip_offset.h595 #define GC_BASE__INST1_SEG0 0 macro
H A Dvega10_ip_offset.h851 #define GC_BASE__INST1_SEG0 0 macro
H A Drenoir_ip_offset.h619 #define GC_BASE__INST1_SEG0 0 macro
H A Dvangogh_ip_offset.h683 #define GC_BASE__INST1_SEG0 0 macro
H A Dyellow_carp_offset.h637 #define GC_BASE__INST1_SEG0 0 macro
H A Darct_ip_offset.h477 #define GC_BASE__INST1_SEG0 0 macro
H A Daldebaran_ip_offset.h520 #define GC_BASE__INST1_SEG0 0 macro